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AD9558 Datasheet(PDF) 6 Page - Analog Devices

Part # AD9558
Description  Quad Input Multiservice Line Card Adaptive Clock Translator with Frame Sync
PDF  105 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9558 Datasheet(HTML) 6 Page - Analog Devices

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AD9558
Data Sheet
Rev. C | Page 6 of 105
POWER DISSIPATION
Table 3.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER DISSIPATION
Typical Configuration
0.47
0.74
1.02
W
System clock: 49.152 MHz crystal; DPLL active;
both 19.44 MHz input references in differential mode;
one HSTL driver at 644.53125 MHz;
one 3.3 V CMOS driver at 161.1328125 MHz and 80 pF
capacitive load on CMOS output
All Blocks Running
0.6
1.0
1.32
W
System clock: 49.152 MHz crystal; DPLL active;
both input references in differential mode;
four HSTL drivers at 750 MHz;
four 3.3 V CMOS drivers at 250 MHz and 80 pF capacitive
load on CMOS outputs
Full Power-Down
44
125
mW
Typical configuration with no external pull-up or pull-down
resistors; approximately 2/3 of this power is on AVDD3
Incremental Power Dissipation
Conditions = typical configuration; table values show the
change in power due to the indicated operation
Input Reference On/Off
Differential Without Divide-by-2
20
25
32
mW
Additional current draw is in the DVDD3 domain only
Differential With Divide-by-2
26
32
40
mW
Additional current draw is in the DVDD3 domain only
Single-Ended (Without Divide-by-2)
5
7
9
mW
Additional current draw is in the DVDD3 domain only
Output Distribution Driver On/Off
LVDS (at 750 MHz)
12
17
22
mW
Additional current draw is in the AVDD domain only
HSTL (at 750 MHz)
14
21
28
mW
Additional current draw is in the AVDD domain only
1.8 V CMOS (at 250 MHz)
14
21
28
mW
A single 1.8 V CMOS output with an 80 pF load
3.3 V CMOS (at 250 MHz)
18
27
36
mW
A single 3.3 V CMOS output with an 80 pF load
Other Blocks On/Off
Second RF Divider
36
51
64
mW
Additional current draw is in the AVDD domain only
Channel Divider Bypassed
10
17
23
mW
Additional current draw is in the AVDD domain only
LOGIC INPUTS (SYNC, RESET, PINCONTROL, M7 TO M0)
Table 4.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LOGIC INPUTS (SYNC, RESET, PINCONTROL)
Input High Voltage (VIH)
2.1
V
Input Low Voltage (VIL)
0.8
V
Input Current (IINH, IINL)
±50
±100
µA
Input Capacitance (CIN)
3
pF
LOGIC INPUTS (M7 to M0)
Input High Voltage (VIH)
2.5
V
Input ½ Level Voltage (VIM)
1.0
2.2
V
Input Low Voltage (VIL)
0.6
V
Input Current (IINH, IINL)
±60
±100
µA
Input Capacitance (CIN)
3
pF



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