PRELIMINARY

Rev F

PRELIMINARY

11

CPC5750

2.1 Mode Control Register

This register allows the programmable control of the Companding, analog and digital loop backs for debug testing,

Power Down mode, and custom control of the PCM interface.

2.1.1 Companding (bit 7)

This bit determines the data compression method to be used. The value of this bit during Power Up or Reset is

determined by the level on CS (pin 7) when the chip reset goes inactive. During either of these events the logical

level on CS must be maintained for a minimum duration of 40

s. For Power Up, the hold time begins with a valid

RST. Once active, this bit can be modified using the SPI interface (PCM Mode) or the GCI link (IOM-2 GCI Mode).

The bit values to set the compression method are:

Logic '0':

-law

Logic '1': A-law

2.1.2 ALB (bit 5)

The Analog Loop Back (ALB) bit is used to test the analog interface of the CPC5750 by connecting the output of

the analog input amplifier to the input of the analog output amplifier. To prevent received digital information from

interfering with the test, the connection between the DAC and the input of the analog output amplifier is opened.

the analog to digital transmit path remains intact, allowing the means to monitor the analog input gain. The bit

values to activate and de-activate the Analog Loop Back are:

Logic '0': Normal Operation (Analog Loop Back disabled)

Logic '1': Analog Loop Back Mode

2.1.3 DLB (bit 4)

The Digital Loop Back (DLB) bit is used to test the digital interfaces, (PCM or GCI) and the DSP sections of the

CPC5750 by separating the transmit path analog input section and ADC from the transmit DSP section and

connecting the digital output of the receive path DSP to the digital input of the transmit path DSP. This provides an

all-digital test path through the receive path’s DAC filters and Noise Shaper and back out through ADC digital

filters. The DLB configuration retains the connection between the receive path’s digital and analog sections

bit values to control the Digital Loop Back function are:

Logic '0': Normal Operation (Digital Loop Back disabled)

Logic '1': Digital Loop Back Mode

2.1.4 PD (bit 3)

The Power-Down (PD) bit is used to put the CPC5750 in a standby mode where it draws very little current.

Logic '0': Normal Operation

Logic '1': Device is Powered Down. The SPI bus interface (PCM Mode) and GCI link (GCI Mode)

are still functional to allow enabling the part. The GCI interface will draw current if clocked

Register

7

6

5

4

3

2

1

0

Address

Mode Control

Companding

Not Used

ALB

DLB

PD

CPB

TXZ

TM

0x0

Default

(CS Level at Reset)

0001000

-