PRELIMINARY

18

PRELIMINARY

Rev F

CPC5750

5. PCM Bus Interface

(eight bits) of

-law or A-law companded audio data every cycle of the 8kHz Frame Sync (FS) clock. This provides for

a 64k bit per second data rate in each direction. Provided within each frame (cycle of the FS clock) are a number of

8-bit time slots determined by the frequency of PCLK and the value assigned to the CPB bit in the Mode Control

register. The number of available time slots is calculated as the PCLK frequency (variable) divided by the FS

frequency (fixed at 8kHz) divided by the number of PCLK cycles per data byte (variable, 8 or 16 controlled by CPB).

The relationship between the PCLK frequency and CPB to the number of available PCM time slots is shown in

Table 2: PCLK Frequencies and Available PCM Time Slots.

Capable of transmitting (upstream) and receiving (downstream) in separate time slots, the CPC5750 PCM upstream

and downstream data paths can be provisioned independently to any of the available time slots within the frame.

Additionally, the upstream and downstream paths can be provisioned independently for bit delays within the time slot.

While the non-delayed timing mode does not have bit delays, the delayed timing mode does. To provide for bit delays

within the system, the CPC5750 allows the user to provision the time slot starting point to any of the possible bits

within the 125

s frame. This requires 10 bits to accommodate the device’s 128 maximum time slots. The lower 3 bits

used to modify the start bit (MSB) position within a time slot is in a separate register from the time slot assignment

register to ease provisioning for applications that require setting only the 8-bit time slot or just the bit delay, allowing

the other register to be ignored.

onto a common bus. Since other devices assigned to different time slots transmit their upstream data onto this same

outputs 8-bits of data is contingent upon the value set in the Mode Control register’s TXZ bit. For provisioning details

see Section 2.1.6 TXZ (bit 1) and Section 2.1.5 CPB (bit 2) beginning on page 12.

Time slot locations within the transmit and receive data bit streams are defined by the location of the Frame

Synchronization (FS) pulse and the value set in bit delay registers as described in Section 2.9 PCM Interface DTX

Bit Delay Register and Section 2.7 PCM Interface DRX Bit Delay Register beginning on page 13. Historically,

timing of data bit streams was defined by two modes, Non-delayed Timing Mode and Delayed Timing Mode by means

of a Long Frame Sync pulse and a Short Frame Sync pulse to establish a reference point for the first bit of the first

time slot of the frame.

The Non-delayed Timing Mode used the Long Frame Sync as an enable to define the location of the time slot. The

first data bit of the Long Frame Sync time slot was defined as the first concurrent logic high of the PCM clock and the

frame sync pulse. In this configuration there is no requirement for the rising edge of the clock or the sync pulse to

precede the other. Because the Long Frame Sync pulse is an enable, the width of pulse needs to be sufficient to

ensure data transfer of all eight bits.

The Delayed Timing Mode used the Short Frame Sync to establish the beginning of the first time slot within the frame.

This method used the first falling edge of the PCM clock to register the frame synchronization pulse marking the end

of the current frame. With the conclusion of the current frame, the first bit of the next frame begins with the next rising

edge of the PCM clock. Because this method provides an indicator prior to the beginning of the frame it is ideal for use

in systems wishing to delay data transfer.

The CPC5750 uses a timing mode that is compatible with both of these legacy techniques. Interoperability is assured

by the internal timing circuitry and the device’s ability to access the data bit stream at any point within the frame. In the

CPC5750, the first bit of the frame is defined as coincident with the PCLK rising edge preceding the falling PCLK

edge used to detect the active FS pulse.