PRELIMINARY

Rev F

PRELIMINARY

15

CPC5750

3. Digital Transmission Modes: PCM or IOM-2 GCI

The CPC5750 was designed to be used in communication systems utilizing either the traditional PCM bus method of

digital transmission flow or the newer IOM-2 GCI bus. Both operational modes make use of the 4-wire digital

transmission bus consisting of the data clock (PCLK), an 8kHz Frame Synchronization clock (FS), an upstream

data structure within the digital transmit and receive streams is dissimilar.

One major difference between the PCM Mode and the GCI Mode of operation is how provisioning, control and status

is implemented. When operating in the PCM Mode a serial (SPI) bus is utilized to perform these functions. In the GCI

Mode these functions are embedded in the transmit and receive data streams, thereby eliminating the need for an

additional bus for command and control.

3.1 Digital Transmission Mode Selection

Configuring the CPC5750 to operate in PCM or GCI Mode is performed during either a Power Up or Reset event

using the level at the SDI input pin to determine the mode. Holding SDI high will cause the CPC5750 to be placed into

the PCM Mode of operation while holding SDI low will result in the GCI Mode.

For PCM applications, the voltage available at SDI during power up may not satisfy the specified logic high threshold

voltage stated in Section 1.7 Digital Interface Characteristics on page 6. To ensure a logic high is recognized at

Because the GCI Mode does not utilize the SPI bus, those applications should tie the SDI input low and the CS input

to the appropriate logic level dependent on the desired companding. The companding method set by CS during

Power Up or Reset can be overridden by provisioning bit 7 of the Mode Control register.

3.2 PCLK Frequencies and Time Slot Selection

The clocking circuits use the Frame Sync (FS) signal from the PCM or IOM-2 bus to automatically determine the

PCLK frequency and divides or multiplies the clock as necessary to generate an on-chip 1.024MHz clock.

The table below shows the allowed PCLK frequencies for both the PCM and GCI Modes and the time slot allocations.

For the PCM Mode there are eight allowed PCLK frequencies while the IOM-2 GCI Mode has only two. When using

the PCM Mode, the maximum number of available time slots is dependent on the number of eight bit channels that

can be transferred within one period of the 8kHz Frame Sync clock. For all systems, the maximum number of time

slots is the PCLK frequency divided by the Frame Sync frequency divided by the number of clock bits (pulses) per

channel. A system that uses one clock bit for each transmission bit, the number of time slots is the PCLK frequency

divided by 8kHz divided by 8 clock pulses which is PCLK / 64kHz. PCM systems using two PCLK pulses per

transmission bit will need to set bit 2 of the Mode Control register to a logic 1. Calculating the number of time slots is

now PCLK frequency / 128kHz. The table below provides a quick reference.

Assignment of the specific time slot to be used when in PCM Mode is done by provisioning the PCM transmit and

receive time slot assignment registers described in Section 2.8 and Section 2.6 beginning on page 13.

Only two PCLK frequencies are allowed for the IOM-2 GCI Mode and the number of available time slots is

independent of the clock frequency. Because the number of time slots in GCI Mode is fixed and the higher allowed

frequency is twice the lower allowed frequency, the CPC5750 will use two PCLK bits per transmission bit when it

detects the higher allowed PCLK frequency. This is shown in the following table.

Available time slots for the IOM-2 GCI Mode is based on the number of available sub-frames. The IOM-2 GCI

definition provides for eight sub-frames within a single frame defined by the time period of the Frame Sync clock.