PRELIMINARY

Rev F

PRELIMINARY

25

CPC5750

Figure 9: GCI Interface Timing with 2x PCLK

6.1 Monitor Channel Operations

The Monitor (M) channel is used for reading and writing the CPC5750's registers. The Monitor channel requires the

use of the MR and MX bits in the SC channel for handshaking.

All Monitor channel transfers are in the following format:

1.

Device Address: 0x91 for normal transfers, 0x90 for the special “Channel Identification Command”

2.

Command: 0x81 for a read, 0x01 for a write, 0x00 for the “Channel Identification Command”

3.

Address: 0x0 - 0xA corresponding to register address in Table 1: Control Registers (Not sent for “Channel

Identification Command”)

4a. Write commands follow the address with up to 11 data bytes

4b. Read commands terminate after the address, and are followed by a write sequence (controlled by the CPC5750)

that transfers data to the host device

4c. The special “Channel Identification Command” is terminated after the command byte is sent

(The CPC5750 responds by controlling a write sequence to the host of two fixed bytes: 0x90, 0xB8)

Before a Monitor channel command can be started by the host device, the MX and MR bits must be inactive (high) for

at least two frames. To initiate a transfer of data by the host device, the MX bit should be set active by the external

controller. This signals the CPC5750 to look for a transmission on the Monitor channel. To confirm that the data was

received, the CPC5750 asserts the MR bit. Once confirmation is complete, the external controller makes the MX

inactive for one frame, then, if it is to continue to transmit, it sets the MX bit active again; otherwise, it ends the

message by leaving the MX bit inactive for another frame.

t

FHD

t

PC

t

FSU

t

RXSU

t

RXHD

t

TXDA

t

TXDA

t

FP

t

TRIR

t

TRIF

PCLK

FS

D

RX

D

TX