ADF4196

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

CMR

Common-Mode Reference Voltage for the Output Voltage Swing of the Differential Amplifier. Internally biased to

three-fifths of V

2

A

OUT

Differential Amplifier Output. This pin is the differential amplifier output to tune the external VCO.

3

SW3

Fast Lock Switch 3. This switch is closed when the SW3 timeout counter is active.

4

A

Analog Ground. This is the ground return pin for the differential amplifier and the RF section.

5

RF

IN−

Complementary Input to the RF Prescaler. This pin must be decoupled to the ground plane with a small bypass

capacitor, typically 100 pF.

6

RF

IN+

Input to the RF Prescaler. This small-signal input is ac-coupled to the external VCO.

7

AV

DD

Power Supply Pin for the RF Section. Nominally 3 V. Place a 100 pF decoupling capacitor to the ground plane as

close as possible to this pin.

8

DV

Power Supply Pin for the N Divider. DV

capacitor to the ground plane as close as possible to this pin.

9

D

Ground Return Pin for DV

10

DV

Power Supply Pin for the REF

ground plane as close as possible to this pin.

11

REF

IN

Reference Input. This CMOS input has a nominal threshold of V

This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.

12

D

Ground Return Pin for DV

13

DV

Power Supply Pin for the Serial Interface Logic. Nominally 3 V.

14

SD

GND

Ground Return Pin for the Digital Σ-Δ Modulator.

15

SDV

DD

Power Supply Pin for the Digital Σ-Δ Modulator. Nominally 3 V. Place a 0.1 µF decoupling capacitor to the ground

plane as close as possible to this pin.

16

MUX

OUT

Multiplexer Output. This multiplexer output allows the lock detect, the scaled RF, or the scaled reference frequency

to be accessed externally (see Figure 35 for details).

17

CLK

Serial Clock Input. Data is clocked into the 24-bit shift register on the CLK rising edge. This input is a high

impedance CMOS input.

18

DATA

Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high

impedance CMOS input.

19

LE

Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register that is

selected by the three LSBs.

20

V

Power Supply Pin for the Phase Frequency Detector (PFD). Nominally 5 V, V

Place a 0.1 µF decoupling capacitor to the ground plane as close as possible to this pin.

21

D

Ground Return Pin for V

22

A

Ground Return Pin for V

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

LE

DATA

CLK

ADF4196

TOP VIEW

(Not to Scale)

PIN 1

INDICATOR

CMR

SW3

NOTES

1. THE EXPOSED PADDLE MUST BE CONNECTED

TO THE GROUND PLANE.

Rev. D | Page 6 of 28