ADF4196 datasheet(10/28 Pages) AD

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ADF4196

Data Sheet

Rev. D | Page 10 of 28

Figure 16. Voltage Noise Density Measured at the

Differential Amplifier Output

Figure 17. On Resistance of the SW1, SW2, and SW3 Loop Filter Switches

Figure 18. Detected RF Output Phase for Phase Code Sweep from 0 to MOD

Figure 19. Test Setup for Phase Lock Time Measurements

FREQUENCY (Hz)

10k

100k

100

1000

10M

7nV/ Hz @ 20kHz

DRAIN VOLTAGE (V)

234

100

+85°C

SW3

–40°C

+25°C

–40°C

+25°C

+85°C

SW1,

SW2

TUNING VOLTAGE RANGE

PHASE CODE

1.8

1.5

1.2

0.9

0.6

0.3

130

117

104

MEASURED USING AD8302 PHASE DETECTOR

Y-AXIS SCALE: 10mV/DEGREE

RF = 1880MHz, PFD = 26MHz, MOD = 130

X-AXIS SCALE: 2.77°/STEP

INTERVAL BETWEEN R0 WRITES SHOULD BE A MULTIPLE OF MOD

REFERENCE CYCLES (5µs) FOR COHERENT PHASE MEASUREMENTS

SIGNAL

GENERATOR

OSCILLOSCOPE

ADF4193

EVAL BOARD

104MHz

5dBm

10MHz

EXT REF

1880MHz

1805MHz

1880MHz

RFOUT

REFIN

SIGNAL

GENERATOR

INPA

AD8302

EVB

VPHS

INPB

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