ADF4196 datasheet(22/28 Pages) AD

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ADF4196

Data Sheet

PROGRAMMING THE ADF4196

The ADF4196 can synthesize output frequencies with a channel

step or resolution that is a fraction of the input reference fre-

quency. For a given input reference frequency and a desired

output frequency step, the first choice to make is the PFD

reference frequency and the MOD value. After these are chosen,

the desired output frequency channels are set by programming

the INT and FRAC values.

WORKED EXAMPLE

In this example of a GSM900 Rx system, the RF output frequencies

must be generated with channel steps of 200 kHz. A reference

frequency input (REFIN) of 104 MHz is available. The R divider

setting that determines the PFD reference is shown in Equation 3.

fPFD = REFIN × [(1 + D)/(R × (1 + T))]

(3)

where:

REFIN is the input reference frequency.

D is the doubler enable bit (0 or 1).

R is the 4-bit R counter code (1 to 15).

T is the REF/2 bit (0 or 1).

The maximum PFD reference frequency of 26 MHz is chosen,

and the following settings are programmed to give an R divider

value of 4:

•

Doubler enable = 0

•

R = 2

•

REF/2 = 1

Next, the modulus is chosen to allow fractional steps of 200 kHz:

MOD = 26 MHz/200 kHz = 130

(4)

When the channel step is defined, Equation 5 shows how output

frequency channels are programmed.

RFOUT = [INT + (FRAC/MOD)] × fPFD

(5)

where:

RFOUT is the desired RF output frequency.

INT is the integer part of the division.

FRAC is the numerator part of the fractional division.

MOD is the modulus or denominator part of the fractional

division.

Thus, the frequency channel at 962.4 MHz is synthesized by

programming the following values: INT = 37 and FRAC = 2.

SPUR MECHANISMS

The following sections describe the three different spur

mechanisms that arise with a fractional-N synthesizer and how

the ADF4196 can best be programmed to minimize them.

Fractional Spurs

The fractional interpolator in the ADF4196 is a third-order, Σ-Δ

modulator (SDM) with a modulus MOD that is programmable

to any integer value from 13 to 4095. If dither is enabled, the

minimum allowed value of MOD is 50. The SDM is clocked at

the PFD reference rate (fPFD), which allows PLL output frequencies

to be synthesized at a channel step resolution of fPFD/MOD.

With dither turned off, the quantization noise from the Σ-Δ

modulator appears as fractional spurs. The interval between spurs

is fPFD/L, where L is the repeat length of the code sequence in

the digital Σ-Δ modulator. For the third-order modulator used

in the ADF4196, the repeat length depends on the value of

MOD, as shown in Table 8.

Table 8. Fractional Spurs with Dither Off

Condition (Dither Off)

Repeat

Length

Spur Interval

MOD Is Divisible by 2 but Not by 3

2 × MOD

Channel step/2

MOD Is Divisible by 3 but Not by 2

3 × MOD

Channel step/3

MOD Is Divisible by 6

6 × MOD

Channel step/6

All Other Divisors

MOD

Channel step

With dither enabled, the repeat length is extended to 221 cycles,

regardless of the value of MOD, which makes the quantization

error spectrum look like broadband noise. This can degrade the

in-band phase noise at the PLL output by as much as 10 dB.

Therefore, for lowest noise, dither off is a better choice, particularly

when the final loop bandwidth is low enough to attenuate even

the lowest frequency fractional spur. The wide loop bandwidth

range that is available with the ADF4196 allows the use of dither

in most applications.

Integer Boundary Spurs

Another mechanism for fractional spur creation involves

interactions between the RF VCO frequency and the reference

frequency. When these frequencies are not integer related

(which is the purpose of a fractional-N synthesizer), spur

sidebands appear on the VCO output spectrum at an offset

frequency that corresponds to the beat note or difference

frequency between an integer multiple of the reference and

the VCO frequency.

These spurs are attenuated by the loop filter and are more

noticeable on channels that are close to integer multiples of the

reference, where the difference frequency can be inside the loop

bandwidth (thus, the name integer boundary spurs).

The 8:1 loop bandwidth switching ratio of the ADF4196 makes

it possible to attenuate all spurs to sufficiently low levels for most

applications. The final loop bandwidth can be chosen to ensure

that all spurs are far enough out of band and meet the lock time

requirements with the 8× bandwidth boost.

The programmable modulus and R divider of the ADF4196 can

also be used to avoid integer boundary channels. This option is

described in the Avoiding Integer Boundary Channels section.

Rev. D | Page 22 of 28

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