ADF4196 datasheet(20/28 Pages) AD

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ADF4196

Data Sheet

Rev. D | Page 20 of 28

POWER-DOWN REGISTER (R5) BIT MAP

Figure 34. Bit Map for Register R5

R5, the power-down register, can be used to power down the PLL

and differential amplifier sections. After power is initially applied,

Then, before the ADF4196 comes out of power-down, the R2,

R1, and R0 registers must be programmed.

Control Bits

Power-Down Differential Amplifier

When the DB7 and DB6 bits are set to 1, the differential

amplifier is put into power-down. When DB7 and DB6 are set

to 0, normal operation resumes.

Power-Down Charge Pump

Setting Bit DB5 to 1 activates a charge pump power-down, and

the following events occur:



All active dc current paths are removed, except for the

differential amplifier.



The R and N divider counters are forced to their load state

conditions.



The charge pump is powered down with its outputs in

three-state mode.



The digital lock detect circuitry is reset.



The RFIN input is debiased.



The reference input buffer circuitry is disabled.



The serial interface remains active and capable of loading

and latching data.

For normal operation, set Bit DB5 to 0, followed by a write to R0.

CP Three-State

When the CP three-state bit is set to 1, the charge pump outputs

enter three-state. Setting the CP three-state bit to 0 enables the

charge pump outputs.

Counter Reset

When the counter reset bit is set to 1, the counters are held in reset.

For normal operation, set this bit to 0, followed by a write to R0.

DB7

DB6

DB5

DB4

DB3

DB2

C3 (1)

DB1

C2 (0)

DB0

C1 (1)

CONTROL

BITS

DIFF AMP

DISABLED

ENABLED

DIFF AMP

POWER-DOWN

NORMAL OPERATION

3-STATE ENABLED

CHARGE PUMP

3-STATE

NORMAL OPERATION

COUNTER RESET

DISABLED

ENABLED

CHARGE PUMP

POWER-DOWN

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