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LPC47M192 Datasheet(PDF) 14 Page - SMSC Corporation |
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LPC47M192 Datasheet(HTML) 14 Page - SMSC Corporation |
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14 / 228 page ![]() SMSC DS – LPC47M192 Page 14 Rev. 03/30/05 DATASHEET QFP PIN# NAME DESCRIPTION BUFFER NAME PWR WELL NOTES SERIAL PORT 1 INTERFACE (8) 84 RXD1 Receiver serial data input for port 1. IS VCC 85 TXD1 Transmit serial data output for port 1. O12 VCC 87 nRTS1 Active low Request to Send outputs for the Serial Port. Handshake output signal notifies modem that the UART is ready to transmit data. This signal can be programmed by writing to bit 1 of the Modem Control Register (MCR). The hardware reset will reset the nRTS signal to inactive mode (high). nRTS is forced inactive during loop mode operation. O8 VCC 88 nCTS1 Active low Clear to Send inputs for the serial port. Handshake signal which notifies the UART that the modem is ready to receive data. The CPU can monitor the status of nCTS signal by reading bit 4 of Modem Status Register (MSR). A nCTS signal state change from low to high after the last MSR read will set MSR bit 0 to a 1. If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when nCTS changes state. The nCTS signal has no effect on the transmitter. Note: Bit 4 of MSR is the complement of nCTS. I VCC 89 nDTR1 Active low Data Terminal Ready outputs for the serial port. Handshake output signal notifies modem that the UART is ready to establish data communication link. This signal can be programmed by writing to bit 0 of Modem Control Register (MCR). The hardware reset will reset the nDTR signal to inactive mode (high). nDTR is forced inactive during loop mode operation. O6 VCC 86 nDSR1 Active low Data Set Ready input for the serial port. Handshake signal which notifies the UART that the modem is ready to establish the communication link. The CPU can monitor the status of nDSR signal by reading bit 5 of Modem Status Register (MSR). A nDSR signal state change from low to high after the last MSR read will set MSR bit 1 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nDSR changes state. Note: Bit 5 of MSR is the complement of nDSR. I VCC |
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