LPC47M192 datasheet(99/228 Pages) SMSC

99 / 228 page

SMSC DS – LPC47M192

Page 99

Rev. 03/30/05

DATASHEET

Wake Up From Auto Powerdown

If the part enters the powerdown state through the auto powerdown mode, then the part can be awakened by reset or

by appropriate access to certain registers.

If a hardware or software reset is used then the part will go through the normal reset sequence. If the access is

through the selected registers, then the FDC resumes operation as though it was never in powerdown. Besides

activating the PCI_RESET# pin or one of the software reset bits in the DOR or DSR, the following register accesses

will wake up the part:

Enabling any one of the motor enable bits in the DOR register (reading the DOR does not awaken the part).

A read from the MSR register.

A read or write to the Data register.

Once awake, the FDC will reinitiate the auto powerdown timer for 10 ms. The part will powerdown again when all

the powerdown conditions are satisfied.

Table 46illustrates the AT and PS/2 (including Model 30) configuration registers available and the type of access

permitted. In order to maintain software transparency, access to all the registers must be maintained. As Table 46

shows, two sets of registers are distinguished based on whether their access results in the part remaining in

powerdown state or exiting it.

Access to all other registers is possible without awakening the part. These registers can be accessed during

powerdown without changing the status of the part. A read from these registers will reflect the true status as shown

in the register description in the FDC description. A write to the part will result in the part retaining the data and

subsequently reflecting it when the part awakens. Accessing the part during powerdown may cause an increase in

the power consumption by the part. The part will revert back to its low power mode when the access has been

completed.

Pin Behavior

The LPC47M192 is specifically designed for systems in which power conservation is a primary concern. This makes

the behavior of the pins during powerdown very important.

The pins of the LPC47M192 can be divided into two major categories: system interface and floppy disk drive

interface. The floppy disk drive pins are disabled so that no power will be drawn through the part as a result of any

voltage applied to the pin within the part’s power supply range. Most of the system interface pins are left active to

monitor system accesses that may wake up the part.

Table 46 - PC/AT and PS/2 Available Registers

AVAILABLE REGISTERS

BASE +

ADDRESS

PC-AT

PS/2 (MODEL 30)

ACCESS PERMITTED

Access to these registers DOES NOT wake up the part

00H

----

SRA

01H

----

SRB

02H

DOR (1)

R/W

03H

---

04H

DSR (1)

06H

---

07H

DIR

07H

CCR

Access to these registers wakes up the part

04H

MSR

05H

Data

R/W

Note 1: Writing to the DOR or DSR does not wake up the part, however, writing any of the motor enable bits or

doing a software reset (via DOR or DSR reset bits) will wake up the part.

System Interface Pins

Table 47 gives the state of the interface pins in the powerdown state. Pins unaffected by the powerdown are labeled

“Unchanged.”

LPC47M192 Datasheet(PDF) 99 Page - SMSC Corporation

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