LPC47M192 datasheet(90/228 Pages) SMSC

90 / 228 page

SMSC DS – LPC47M192

Page 90

Rev. 03/30/05

DATASHEET

to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte the specified number of

times. Hardware support for compression is optional.

Table 41 – ECP Pin Descriptions

NAME

TYPE

DESCRIPTION

nStrobe

During write operations nStrobe registers data or address into the slave

on the asserting edge (handshakes with Busy).

PData 7:0

I/O

Contains address or data or RLE data.

nAck

Indicates valid data driven by the peripheral when asserted. This signal

handshakes with nAutoFd in reverse.

PeriphAck (Busy)

This signal deasserts to indicate that the peripheral can accept data. This

signal handshakes with nStrobe in the forward direction. In the reverse

direction this signal indicates whether the data lines contain ECP

command information or data. The peripheral uses this signal to flow

control in the forward direction. It is an “interlocked” handshake with

nStrobe. PeriphAck also provides command information in the reverse

direction.

PError

(nAckReverse)

Used to acknowledge a change in the direction the transfer (asserted =

forward).

The peripheral drives this signal low to acknowledge

nReverseRequest.

“interlocked”

handshake

with

nReverseRequest. The host relies upon nAckReverse to determine when

it is permitted to drive the data bus.

Select

Indicates printer on line.

nAutoFd

(HostAck)

Requests a byte of data from the peripheral when asserted, handshaking

with nAck in the reverse direction. In the forward direction this signal

indicates whether the data lines contain ECP address or data. The host

drives this signal to flow control in the reverse direction. It is an

“interlocked” handshake with nAck. HostAck also provides command

information in the forward phase.

nFault

(nPeriphRequest)

Generates an error interrupt when asserted. This signal provides a

mechanism for peer-to-peer communication. This signal is valid only in

the forward direction. During ECP Mode the peripheral is permitted (but

not required) to drive this pin low to request a reverse transfer. The

request is merely a “hint” to the host; the host has ultimate control over

the transfer direction. This signal would be typically used to generate an

interrupt to the host CPU.

nInit

Sets the transfer direction (asserted = reverse, deasserted = forward).

This pin is driven low to place the channel in the reverse direction. The

peripheral is only allowed to drive the bi-directional data bus while in

ECP Mode and HostAck is low and nSelectIn is high.

nSelectIn

Always deasserted in ECP mode.

The register definitions are based on the standard IBM addresses for LPT. All of the standard printer ports are

supported. The additional registers attach to an upper bit decode of the standard LPT port definition to avoid conflict

with standard ISA devices. The port is equivalent to a generic parallel port interface and may be operated in that

mode. The port registers vary depending on the mode field in the ecr. The table below lists these dependencies.

Operation of the devices in modes other that those specified is undefined.

Table 42 - ECP Register Definitions

NAME

ADDRESS (Note 1)

ECP MODES

FUNCTION

data

+000h R/W

000-001

Data Register

ecpAFifo

+000h R/W

011

ECP FIFO (Address)

dsr

+001h R/W

All

Status Register

dcr

+002h R/W

All

Control Register

cFifo

+400h R/W

010

Parallel Port Data FIFO

ecpDFifo

+400h R/W

011

ECP FIFO (DATA)

tFifo

+400h R/W

110

Test FIFO

cnfgA

+400h R

111

Configuration Register A

cnfgB

+401h R/W

111

Configuration Register B

ecr

+402h R/W

All

Extended Control Register

LPC47M192 Datasheet(PDF) 90 Page - SMSC Corporation

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