LPC47M192 datasheet(88/228 Pages) SMSC

88 / 228 page

SMSC DS – LPC47M192

Page 88

Rev. 03/30/05

DATASHEET

If nWAIT is asserted, the chip inserts wait states into I/O write cycle until the peripheral deasserts

nWAIT or a time-out occurs.

The chip drives the final sync, deasserts nDATASTB or nADDRSTRB and latches the data from the

internal data bus for the PData bus.

Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.

EPP 1.7 Read

The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. The chip inserts wait

states into the I/O read cycle when nWAIT is active low during the EPP cycle. This can be used to extend the cycle

time. The read cycle can complete when nWAIT is inactive high.

Read Sequence of Operation

The host sets PDIR bit in the control register to a logic “1”. This deasserts nWRITE and tri-states the

PData bus.

The host initiates an I/O read cycle to the selected EPP register.

Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the

nWRITE signal is valid.

If nWAIT is asserted, the chip inserts wait states into the I/O read cycle until the peripheral deasserts

nWAIT or a time-out occurs.

The Peripheral drives PData bus valid.

The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination

phase of the cycle.

The chip drives the final sync and deasserts nDATASTB or nADDRSTRB.

Peripheral tri-states the PData bus.

Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.

Table 40 - EPP Pin Descriptions

EPP

SIGNAL

EPP NAME

TYPE

EPP DESCRIPTION

nWRITE

nWrite

This signal is active low. It denotes a write operation.

PD<0:7>

Address/Data

I/O

Bi-directional EPP byte wide address and data bus.

INTR

Interrupt

This signal is active high and positive edge triggered. (Pass

through with no inversion, Same as SPP).

nWAIT

nWait

This signal is active low.

It is driven inactive as a positive

acknowledgement from the device that the transfer of data is

completed. It is driven active as an indication that the device

is ready for the next transfer.

nDATASTB

nData Strobe

This signal is active low.

It is used to denote data read or

write operation.

nRESET

nReset

This signal is active low.

When driven active, the EPP

device is reset to its initial operational mode.

nADDRSTB

Address

Strobe

This signal is active low. It is used to denote address read or

write operation.

Paper End

Same as SPP mode.

SLCT

Printer

Selected

Status

Same as SPP mode.

nERR

Error

Same as SPP mode.

Note 1: SPP and EPP can use 1 common register.

Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For correct

EPP read cycles, PCD is required to be a low.

7.8.2 EXTENDED CAPABILITIES PARALLEL PORT

ECP provides a number of advantages, some of which are listed below. The individual features are explained in

greater detail in the remainder of this section.

High performance half-duplex forward and reverse channel Interlocked handshake, for fast reliable transfer Optional

single byte RLE compression for improved throughput (64:1) Channel addressing for low-cost peripherals Maintains

link and data layer separation Permits the use of active output drivers permits the use of adaptive signal timing

Peer-to-peer capability.

LPC47M192 Datasheet(PDF) 88 Page - SMSC Corporation

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