LPC47M192 datasheet(5/228 Pages) SMSC

5 / 228 page

SMSC DS – LPC47M192

Page 5

Rev. 03/30/05

DATASHEET

7.4.6

FDC Swap Bit .........................................................................................................................................64

7.5

SERIAL PORT (UART)................................................................................................................... 64

7.6

INFRARED INTERFACE................................................................................................................ 77

7.7

MPU-401 MIDI UART ..................................................................................................................... 78

7.7.1

Overview.................................................................................................................................................78

7.7.2

Host Interface .........................................................................................................................................79

7.7.3

MIDI Data Port........................................................................................................................................79

7.7.4

Status Port..............................................................................................................................................79

7.7.4.1

Bit 7 – MIDI Receive Buffer Empty ............................................................................................................... 79

7.7.4.2

Bit 6 – MIDI Transmit Busy ........................................................................................................................... 80

7.7.5

MPU-401 Command Controller ..............................................................................................................81

7.7.6

MIDI UART .............................................................................................................................................82

7.7.7

MPU-401 Configuration Registers ..........................................................................................................82

7.7.7.1

Activate and I/O Base address......................................................................................................................... 83

7.8

PARALLEL PORT .......................................................................................................................... 83

7.8.1

IBM XT/AT Compatible, Bi-Directional and EPP Modes .........................................................................84

7.8.2

Extended Capabilities Parallel Port.........................................................................................................88

7.9

POWER MANAGEMENT............................................................................................................... 98

7.10

SERIAL IRQ ..............................................................................................................................102

7.11

8042 KEYBOARD CONTROLLER DESCRIPTION ..............................................................................105

7.11.1

Keyboard Interface............................................................................................................................106

7.11.2

External Keyboard and Mouse Interface ...........................................................................................107

7.11.3

Keyboard Power Management..........................................................................................................107

7.11.4

Interrupts...........................................................................................................................................108

7.11.5

Memory Configurations .....................................................................................................................108

7.11.6

Register Definitions ...........................................................................................................................108

7.11.6.1

Host I/F Data Register................................................................................................................................... 108

7.11.6.2

Host I/F Status Register................................................................................................................................. 108

7.11.7

External Clock Signal ........................................................................................................................108

7.11.8

Default Reset Conditions ..................................................................................................................109

7.11.9

Keyboard and Mouse PME Generation.............................................................................................112

7.12

GENERAL PURPOSE I/O.........................................................................................................113

7.12.1

GPIO Pins .........................................................................................................................................113

7.12.2

Description ........................................................................................................................................114

7.12.3

GPIO Control.....................................................................................................................................115

7.12.4

GPIO Operation ................................................................................................................................116

7.12.5

GPIO PME and SMI Functionality .....................................................................................................117

7.12.6

Either Edge Triggered Interrupts .......................................................................................................118

7.12.7

LED Functionality ..............................................................................................................................118

7.13

SYSTEM MANAGEMENT INTERRUPT (SMI) .........................................................................118

7.13.1

SMI Registers....................................................................................................................................119

7.14

PME SUPPORT ........................................................................................................................119

7.14.1

‘Wake on Specific Key’ Option ..........................................................................................................120

7.15

FAN SPEED CONTROL AND MONITORING ..........................................................................121

7.15.1

Fan Speed Control ............................................................................................................................121

7.15.2

Fan Speed Monitoring.......................................................................................................................122

7.16

SECURITY FEATURE ..............................................................................................................125

7.16.1

GPIO Device Disable Register Control .............................................................................................125

7.16.2

Device Disable Register....................................................................................................................125

7.17

GAME PORT LOGIC ................................................................................................................125

7.17.1

Power Control Register .....................................................................................................................128

7.17.2

VREF Pin ..........................................................................................................................................128

7.18

HARDWARE MONITORING INTERFACE ...........................................................................................129

7.18.1

Hardware Monitoring Interface Signal Definition ...............................................................................129

7.18.2

SMBus Interface................................................................................................................................129

7.18.2.1

SMBus Slave Interface.................................................................................................................................. 130

7.18.3

Hardware Monitoring Block ...............................................................................................................132

7.18.3.1

Input Monitoring ........................................................................................................................................... 132

7.18.3.2

Resetting the Hardware Monitoring Block.................................................................................................... 132

7.18.3.3

Reset Out Pin ................................................................................................................................................ 133

7.18.3.4

Monitoring Modes......................................................................................................................................... 133

7.18.3.5

Interrupt Status Registers .............................................................................................................................. 134

7.18.3.6

Low Power Modes ........................................................................................................................................ 134

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