LPC47M192 datasheet(102/228 Pages) SMSC

102 / 228 page

SMSC DS – LPC47M192

Page 102

Rev. 03/30/05

DATASHEET

7.10 SERIAL IRQ

The LPC47M192 supports the serial interrupt to transmit interrupt information to the host system. The serial interrupt

scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0.

Timing Diagrams For SER_IRQ Cycle

A) Start Frame timing with source sampled a low pulse on IRQ1

SER_IRQ

PCI_CLK

Host Controller

IRQ1

Drive Source

None

IRQ0 FRAME IRQ1 FRAME

IRQ2 FRAME

None

START

START FRAME

Note:

H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample

Note 1: Start Frame pulse can be 4-8 clocks wide depending on the location of the device in the PCI bridge

hierarchy in a synchronous bridge design.

B) Stop Frame Timing with Host using 17 SER_IRQ sampling period

SER_IRQ

PCI_CLK

Host Controller

IRQ15

Driver

None

IRQ14

IRQ15

IOCHCK#

None

STOP

STOP FRAME

START

NEXT CYCLE

FRAME

Note:

H=Host Control; R=Recovery; T=Turn-Around; S=Sample; I=Idle

Note 1: The next SER_IRQ cycle’s Start Frame pulse may or may not start immediately after the turn-around clock

of the Stop Frame.

Note 2: There may be none, one or more Idle states during the Stop Frame.

Note 3: Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.

SER_IRQ Cycle Control

There are two modes of operation for the SER_IRQ Start Frame

1) Quiet (Active) Mode: Any device may initiate a Start Frame by driving the SER_IRQ low for one clock, while the

SER_IRQ is Idle. After driving low for one clock the SER_IRQ must immediately be tri-stated without at any time

driving high. A Start Frame may not be initiated while the SER_IRQ is Active. The SER_IRQ is Idle between Stop

and Start Frames. The SER_IRQ is Active between Start and Stop Frames. This mode of operation allows the

SER_IRQ to be Idle when there are no IRQ/Data transitions which should be most of the time.

Once a Start Frame has been initiated the Host Controller will take over driving the SER_IRQ low in the next clock

and will continue driving the SER_IRQ low for a programmable period of three to seven clocks. This makes a total

low pulse width of four to eight clocks. Finally, the Host Controller will drive the SER_IRQ back high for one clock,

then tri-state.

Any SER_IRQ Device (i.e., The LPC47M192) which detects any transition on an IRQ/Data line for which it is

responsible must initiate a Start Frame in order to update the Host Controller unless the SER_IRQ is already in an

SER_IRQ Cycle and the IRQ/Data transition can be delivered in that SER_IRQ Cycle

LPC47M192 Datasheet(PDF) 102 Page - SMSC Corporation

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