RSC4128 datasheet(22/49 Pages) ETC

22 / 49 page

RSC-4128

Data Sheet

P/N 80-0206-J

T1 and T3 can generate interrupts upon overflow by setting register FD.Bit0=1 and Bit4=1, respectively. (see

“Interrupts” section)

Timer2

Timer2 (T2) is clocked by CLK2 divided by 128. The overflow pulse from T2 can cause an interrupt request which in

turn will cause a T2 Wake-up from power-down, if register E8.Bit6=1. (see “Power and Wakeup Control” section).

Note that the Timer2 “irq” bit (register FE.Bit1) must be cleared prior to powering down to allow the wakeup

interrupt request to occur. T2 can also generate a standard interrupt request by setting register FD.Bit1=1. (see

“Interrupts” section)

Timers 1, 2 and 3 Timer Reload and Counter Registers

All are cleared to zero on reset.

addr

t1r

EBH

Read/Write

Timer1 Counter Reload (2's complement of period)

t1v

ECH

Read

Timer1 current counter value

Write

Force load of Timer1 counter from reload register

t2r

EDH

Read/Write

Timer2 Counter Reload (2's complement of period)

t2v

EEH

Read

Timer2 current counter value

Write

Force load of Timer2 counter from reload register

t3r

DAH

Read/Write

Timer3 Counter Reload (2's complement of period)

t3v

DBH

Read

Timer3 current counter value

Write

Force load of Timer3 counter from reload register

Multi-Task Timer

The multi-tasking (MT) timer is intended to count a fixed interval of 858.1 microseconds.

This provides a

“heartbeat” for multi-tasking in the Sensory Speech 7 technology library. Other applications may find this useful for

similar purposes. This interval is obtained by dividing the CLK1 rate, when running at 14.32 MHz, by a fixed factor

of 12288. There is no configurability to the MT timer. One bit in the Clock Extension Register (D6.Bit6) enable this

timer’s clock. The MT timer overflow can generate an interrupt by setting register FD.Bit7=1. (see “Interrupts”

section)

Watchdog Timer

Due to static electricity, voltage glitches, or other environmental conditions (or program bugs!), a software program

can begin to operate incorrectly. The watchdog timer provides protection from such errant operation.

The Watchdog Timer (WDT) unit comprises two control bits in the System Control Register (D5), a special

instruction, two status bits, and a 17-bit counter. The counter, driven by OSC2, produces a toggle rate of

approximately 4 seconds at the 17

th bit. A 2-bit decoded mux in the “sysCtl” register (register D5) allows selecting

the WDT timeout pulse from bit 9, 13, 15, or 17 of the counter. This selection sets the timeout in the range of

approximately 15.6 msec to 4 seconds. The accuracy of these times will depend on whether the OSC2 source is a

32 KHz crystal or the on-chip RC.

The WDT is enabled by register FB.Bit4=1. This bit can only be set by execution of the “WDC” instruction. This bit

is cleared by reset, so the WDT is disabled by reset. The bit is also cleared when E8.Bit7=1 (pdn), so the WDT is

disabled in either SLEEP or IDLE mode. It is not automatically re-enabled on Wakeup. Program control cannot

write to register FB.Bit4 to enable or disable the WDT. That is, FB.Bit4 is a read-only bit for normal register access

instructions. Since the WDT needs OSC2 for its operation, once the WDC instruction has been executed and

“pdn” bit (register E8.Bit7) is also set simultaneously. This allows disabling the WDT only when entering a power

down mode and is intended to reduce the probability of accidental software disabling of the WDT in active mode.

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