RSC4128 datasheet(28/49 Pages) ETC

28 / 49 page

RSC-4128

Data Sheet

P/N 80-0206-J

Manual” for more information on Record and Playback) Typical low frequency noise sources include 60 Hz hum,

“motor boating” or cyclical fluctuations in the system power supply from “sagging” due to flash writes during speech

recording, and LED blinking during recording of speech. All of these effects are reduced in speech playback by

using a capacitor closer to 220uF.

NOTE: See Design Notes - “Microphone Housing” and “Selecting Microphone” on the RSC-4x Demo/Evaluation

CD. Improper microphone circuit and/or enclosure design will result in poor recognition performance.

Reset

An external reset is generated by applying a low condition for at least two clock cycles on -RESET, an active low

Schmitt trigger input. The output of the Schmitt trigger passes through a 10 nsec glitch blocking circuit, followed by

an asynchronous flip-flop. The output of the flip-flop generates active high reset throughout RSC-4128. The

internal reset state is held for 20 msec (when clocked by a 14.32 MHz PCLK).

The purpose is to allow the

oscillator to stabilize and the PLL to lock before enabling the processor and the other RSC-4128 circuits.

External reset clears the Global Interrupt Enable flag and begins execution at address 0h. The special function

registers will be cleared, set, or left as-is, as detailed in the “Special Function Registers Summary” section.

Watchdog Timeout Reset

A special Watchdog Timeout Reset is produced if the Watchdog Timer is enabled and the Watchdog counter times

out. The only difference between the Watchdog Timeout Reset and an ordinary reset is that the “wd_timed” bit in

the “sysStat” register (register FB.Bit5) is preserved as “1” for a Watchdog Timeout Reset

Digital-to-Analog-Converter (DAC) Output

The DAC consists of an R-2R network with 10 bits of resolution and an output impedance of approximately 11

Kohms. An external amplifier is required to drive a speaker when using the DAC. The specifications of that

amplifier will determine the best choice of speaker impedance and the resulting volume.

The 10-bit resolution corresponds to an analog voltage range between 0V and Vdd minus 1 LSB (represented as

“Vdd-“). At Vdd=3V, one LSB of the R-2R network corresponds to about 3 mV. For example:

R2R Value

DAC output; Vdd=3V

000H = 0v

0.000V

001H = 0v+

0.003V

200H = Vdd/2 1.500V

3FFH = Vdd-

2.997V

There are two DAC output modes, full-scale and half-scale. In full-scale mode the output voltage swings between

0v and Vdd-; in half-scale mode the output swings between Vdd/4 and 3Vdd/4 minus 1 LSB (roughly Vdd/2 +/-

Vdd/4). Values written into the DAC hold register and certain Analog Control register bits are converted into analog

voltages.

The DAC hold register (“dac”; register FA) presents an 8-bit signed value to the DAC unit. In full-scale mode, the 8

most significant bits are driven by the DAC hold register and the 2 least significant bits are driven by the LSB1 and

LSB0 bits in the Analog Control register (“anCtl”; register EF.Bits[5:4]). This results in a total output range of –512

to +511. In half-scale mode the 8 middle bits of are driven by the DAC hold register, the most significant bit is

generated automatically by sign extension, and the least significant bit is driven by bit LSB1 in the Analog Control

(d2a_half) equal to “1” in register EF.Bit3. The tables below show a selection of values and the resulting output

voltage.

Note: Register EF.Bit7 (“-anctlen”) must be “0” in the value being written to register EF, when writing

EF.Bit2.

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