RSC4128 datasheet(34/49 Pages) ETC

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RSC-4128

Data Sheet

P/N 80-0206-J

ROTATE Group Instructions

Rotate group instructions apply only directly to register space SRAM locations. The carry flag is affected by these

instructions, but the sign and zero flags are unaffected.

Instruction Opcode Operand 1 Operand 2 Description

Bytes

Cycles +Cycles/Waitstate

dest

rotate left, c set from b7

dest

rotate right, c set from b0 2

RLC

dest

rotate left through carry

RRC

dest

rotate right through carry 2

SHL

dest

shift left, c set from b7,

b0=0

SHR

dest

shift right, c set from b0,

b7=0

SAR

dest

shift right arithmetic, c

set from b0, b7

duplicated

BRANCH Group Instructions

The branch instructions use direct address values rather than offsets to define the target address of the branch.

This implies that binary code containing branches is not relocatable. However, object code produced by the RSC-

4128 assembler contains address references that are resolved at link time, so .OBJ modules are relocatable. The

indirect jump instruction uses an 8-bit operand (“@dest”) to designate an SRAM register pointer to the 16-bit target

address. The “dest” pointer register must be at an even address. The LOW byte of the target address is contained

at the pointer address, and the HIGH byte of the target address is contained at the pointer address+1.

Instruction Opcode Operand 1 Operand 2 Description

Bytes Cycles +Cycles/Waitstate

dest low

dest high

jump on carry = 1

JNC

dest low

dest high

jump on carry = 0

dest low

dest high

jump on zflag = 1

JNZ

dest low

dest high

jump on zflag = 0

dest low

dest high

jump on sflag = 1

JNS

dest low

dest high

jump on sflag = 0

JMP

dest low

dest high

jump unconditional

CALL

dest low

dest high

direct subroutine call 3

RET

return from call

IRET

return from interrupt 1

JMPR

@dest

jump indirect

ARITHMETIC/LOGICAL Group Instructions

Arithmetic and logical group instructions apply only to Register Space SRAM locations. The results of the

instruction are always written directly to the SRAM “dest” register. The exceptions are TM and CP instructions,

which do not write the result to the “dest” register and only update the flags register based on the operation’s

outcome. All but the INCrement and DECrement instructions have both register source and immediate source

forms.

In each of the following instructions the sign and zero flags are updated based on the result of the operation. The

carry flag is updated by the arithmetic operations (ADD, ADC, SUB, SUBC, CP, INC, DEC) but it is not affected by

the logical operations (AND, TM, OR, XOR). Note: the carry is set high by SUB, CP, SUBC and DEC when a

borrow is generated.

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