AD5767 datasheet(9/43 Pages) AD

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Data Sheet

AD5766/AD5767

Rev. C | Page 9 of 43

TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2,

Figure 3, and Figure 4. AVCC = 2.97 V to 3.6 V, VLOGIC = 1.7 V to 5.5 V, VREF = 2.5 V, all specifications −40°C to +105°C, dither powered on,

unless otherwise noted.

Table 4.

Parameter

Limit at TMIN, TMAX

Unit

Description

t11

ns min

SCLK cycle time

ns min

SCLK high time

ns min

SCLK low time

ns min

SYNC falling edge to SCLK falling edge setup time

ns min

SCLK falling edge to SYNC rising edge time

ns min

Minimum SYNC high time (write mode)

ns min

Data setup time

ns min

Data hold time

µs typ

DAC output settling time, 32 code step to ±0.5 LSB at 12-bit resolution (see Table 3)

t10

100

ns typ

RESET2 pulse width low

t11

100

ns typ

RESET2 pulse activation time

t12

ns min

SYNC rising edge to SCLK falling edge

t13

ns max

SCLK rising edge to SDO valid (CL_SDO3 = 15 pF)

t14

ns min

Minimum SYNC high time (readback/daisy-chain mode)

t15

µs typ

SYNC rising edge to SYNC rising edge (DAC register updates)

Maximum SCLK frequency is 50 MHz for write mode and 10 MHz for readback mode.

Minimum time between a reset and the subsequent successful write is typically 25

ns.

CL_SDO is the capacitive load on the SDO output.

Timing Diagrams

D23

SCLK

SDI

RESET

VOUT

SYNC

t15

t10

t11

Figure 2. Serial Interface Timing Diagram

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