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USB97C201 Datasheet(PDF) 18 Page - SMSC Corporation |
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USB97C201 Datasheet(HTML) 18 Page - SMSC Corporation |
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18 / 59 page  SMSC DS – USB97C201 Page 18 Rev. 03/25/2002 PRELIMINARY Table 5 - 8051 Core SFR Register Summary These registers are part of the 8051 design core itself. REGISTER BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 ADDRESS SP 81h DPL0 82h DPH0 83h DPL1 84h DPH1 85h DPS 0 0 0 00 00 SEL 86h PCON SMOD0 – 1 1 GF1 GF0 STOP IDLE 87h TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 88h TMOD GATE C/T M1 M0 GATE C/T M1 M0 89h TL0 8Ah TL1 8Bh TH0 8Ch TH1 8Dh CKCON T2M T1M T0M MD2 MD1 MD0 8Eh SPC_ FNC 0 0 00 00 0 WR S 8Fh EXIF IE5 IE4 IE3 IE2 1 0 0 0 91h MPAGE 92h SCON0 SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 98h SBUF0 99h IE EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 A8h IP 1 PS1 PT2 PS0 PT1 PX1 PT0 PX0 B8h TL2 CCh TH2 CDh PSW CY AC F0 RS1 RS0 OV F1 P D0h EICON SMOD1 1 EPFI PFI WDTI 0 0 0 D8h ACC E0h EIE 1 1 1 EWDI EX5 EX4 EX3 EX2 E8h B F0h EIP 1 1 1 PWDI PX5 PX4 PX3 PX2 F8h Notes: Bit WRS of the SPC_FNC register controls the operation of MOVX writes the program or XDATA bus of the 8051. Setting it to 0 ( the reset state), will direct writes to the XDATA bus, either to internal or external destinations, while setting it to 1 will allow writes to the program memory bus to occur, either internally( if the 768 SRAM is the target) or externally. Bits MD2:0 of the CKCON SFR register (8Eh) control the cycle timing for external accesses using the nIOR and nIOW signals. This allows slow peripheral devices to be attached. The values and corresponding strobe widths are shown below: MD2 MD1 MD0 NIOR/NIOW STOBE (CLKS) NIOR/NIOW STROBE (AT 30MHZ) 0 0 0 2 66ns 0 0 1 4 133ns 0 1 0 8 267ns 0 1 1 12 400ns 1 0 0 16 533ns 1 0 1 20 667ns 1 1 0 24 800ns 1 1 1 28 933ns Note: the strobe width will vary with the actual clock divider used for the processor. For example if, 16 Mhz is used, an MD[2:0] value of 111 will result in a 28 clock strobe or 1866ns. |
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