| Electronic Components Datasheet Search |
|
USB97C201 Datasheet(PDF) 30 Page - SMSC Corporation |
|
|
|||||||||||||||||||||||||||||
USB97C201 Datasheet(HTML) 30 Page - SMSC Corporation |
|
30 / 59 page ![]() SMSC DS – USB97C201 Page 30 Rev. 03/25/2002 PRELIMINARY Table 26 - USB Bus Status Register USB_STAT (0xAB - RESET=0x00) USB BUS STATUS REGISTER BIT NAME R/W DESCRIPTION [7] Reserved R This bit always reads “0”. 6 EP2_ERR R/W 1 = Indicates that a token in the opposite direction inferred by the DIR bit of EP2_CTL register was received, ie an unexpected IN or OUT token. 5 2.0 R/W 1 = Host is high speed capable. This bit is set if high speed signaling is received from the host. 4 USB_RESUME R/W 1 = Indicates that RESUME signaling has been detected. This is only valid if the USB97C201 is in the SUSPEND state via bit 0 of the SIE_CONF register. 3 USB_RESET R/W 1 = Indicates that a USB Reset has been detected. 2 ERROR R 1 = Indicates that a USB Error has been detected. See the USB_ERR register for details. This bit is cleared by clearing the USB_ERR register. 1 Reserved R This bit always reads “0”. 0 Reserved R This bit always reads “0”. The bits in this register (except bit 2) are cleared by writing a ‘1’ to the corresponding bit. These bits are ORed, if unMASKED in the USB_MSK register, and drive a latch for the USB_STAT bit in the ISR_0 register. Table 27 – USB Bus Status Mask Register USB_MSK (0xAC - RESET=0xFF) USB BUS STATUS MASK REGISTER BIT NAME R/W DESCRIPTION [7] Reserved R This bit always reads “1”. 6 EP2_ERR R/W 1 = Prevents generation of the USB_STAT bit in the ISR_0 register when the EP2_ERR bit is set in the USB_STAT register. 5 2.0 R/W 1 = Prevents generation of the USB_STAT bit in the ISR_0 register when the 2.0 bit is set in the USB_STAT register. 4 USB_RESUME R/W 1 = Prevents generation of the USB_STAT bit in the ISR_0 register when the USB_RESUME bit is set in the USB_STAT register. 3 USB_RESET R/W 1 = Prevents generation of the USB_STAT bit in the ISR_0 register when the USB_RESET bit is set in the USB_STAT register. 2 ERROR R/W 1 = Prevents generation of the USB_STAT bit in the ISR_0 register when the ERROR bit is set in the USB_STAT register. 1 Reserved R This bit always reads “1”. 0 Reserved R This bit always reads “1”. Note1: The mask bits do not prevent the status in the USB_STAT register from being set, only from setting the USB_STAT bit in the ISR_0 register. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |