USB97C201 datasheet(26/59 Pages) SMSC

26 / 59 page

SMSC DS – USB97C201

Page 26

Rev. 03/25/2002

PRELIMINARY

Table 17 - Utility Configuration Register

UTIL_CONFIG

(9D RESET=0x00)

UTILITY CONFIGURATION REGISTER

BIT

NAME

R/W

DESCRIPTION

SRAMSW

R/W

1 = The 768 byte SRAM is located at 0x0400-

0x06FF in the Code Space, instead of

external Memory.

0 = The 768 byte SRAM is located at 0x0400-

0x06FF in the XDATA space.

Reserved

R/W

Reserved. This bit should never be written to

a “1”.

GPIO0_TOG

R/W

1 = GPIO0 Output Auto Toggle enabled.

0 = Disabled, normal operation occurs.

GPIO4/nWE

R/W

GPIO4/SOF Output Select Mux

0 = GPIO4

1 = The IDE_nIOW signal is output.

GPIO3/T1

R/W

P3.5 Timer 1 input trigger source

0 = GPIO3

1 = TBD

GPIO2/T0

R/W

P3.4 Timer 0 input trigger source

0 = GPIO2

1 = TBD

GPIO1/TXD

R/W

GPIO1/TXD Output Select Mux

0 = GPIO1

1 = P3.1

GPIO0/RXD

R/W

P3.0 RXD/GPIO0 Input Select Mux

0 = RXD<=GPIO0

1 = RXD<='0'

Note 1: GPIO0, when used as an output, will automatically toggle with 1second period and 50% duty cycle if

GPIO0_TOG is high.

Table 18 – SRAM Data Port Register

SRAM_DATA

(0x9F- RESET=0x00)

SRAM DATA PORT

BIT

NAME

R/W

DESCRIPTION

[7:0]

SRAM_DATA

[7:0]

R/W

Data to be read or written

from/to the buffer SRAM. The

address

the

data

determined

the

SRAM_ADD1/2 registers. Data

to be written will be done so

upon

write

this

While reads of the register

always reflects the data at the

memory location.

Table 19 – SRAM Address Register 1

SRAM_ADD1

(A1 RESET=0x00)

SRAM ADDRESS REGISTER 1

BIT

NAME

R/W

DESCRIPTION

[7:0]

SRAM_ADD

[7:0]

R/W

This register contains lower bits

of the address in the buffer

RAM

that

the

SRAM_DATA

USB97C201 Datasheet(PDF) 26 Page - SMSC Corporation

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