USB97C201 datasheet(42/59 Pages) SMSC

42 / 59 page

SMSC DS – USB97C201

Page 42

Rev. 03/25/2002

PRELIMINARY

Table 60 –ATA Slew Rate Control A Register

ATA_SRCA

(0xE5 - RESET=0x00)

ATA SLEW RATE CONTROL A REGISTER

BIT

NAME

R/W

DESCRIPTION

[7:6]

SLEW3

R/W

These two bits are control inputs of the ATA pad for data

bits [15:12]. The bits can be used to vary the slew rate of

IDE_D[15:12] from minimum to maximum rate specified by

the ATA66 specification. The value 11b sets the slew rate

to be the maximum and the value of 00b sets the slew rate

to be the minimum.

[5:4]

SLEW2

R/W

These two bits are control inputs of the ATA pad for data

bits [11:8]. The bits can be used to vary the slew rate of

IDE_D[11:8] from minimum to maximum rate specified by

the ATA66 specification. The value 11b sets the slew rate

to be the maximum and the value of 00b sets the slew rate

to be the minimum.

[3:2]

SLEW1

R/W

These two bits are control inputs of the ATA pad for data

bits [7:4]. The bits can be used to vary the slew rate of

IDE_D[7:4] from minimum to maximum rate specified by the

ATA66 specification. The value 11b sets the slew rate to be

the maximum and the value of 00b sets the slew rate to be

the minimum.

[1:0]

SLEW0

R/W

These two bits are control inputs of the ATA pad for data

bits [3:0]. The bits can be used to vary the slew rate of

IDE_D[3:0] from minimum to maximum rate specified by the

ATA66 specification. The value 11b sets the slew rate to be

the maximum and the value of 00b sets the slew rate to be

the minimum.

Table 61 –ATA Slew Rate Control B Register

ATA_SRCB

(0xE6 - RESET=0x00)

ATA SLEW RATE CONTROL B REGISTER

BIT

NAME

R/W

DESCRIPTION

[7:2]

Reserved

Always returns “0” on reads

[1:0]

SLEW4

R/W

These two bits are control inputs of the ATA pad for

STROBE signaling during Ultra ATA writes to disk. The bits

can be used to vary the slew rate of STROBE from

minimum to maximum rate specified by the ATA66

specification. The value 11b sets the slew rate to be the

maximum and the value of 00b sets the slew rate to be the

minimum.

6.2

SIE Block

The SIE is a USB low-level protocol interpreter.

The SIE controls the USB bus protocol, packet generation /

extraction, PID / Device ID parsing, and CRC coding / decodingwith autonomous error handling.

Parallel-to-serial / serial-to-parallel conversion, bit stuffing, and NRZI coding / decoding are handled in the PHY

block.

It is capable of operating either in USB 1.1 or 2.0 compliant modes. Unlike the normal 97Cxxx series SIEs, it has

more autonomous protocol handling functions like stall condition clearing on setup packets, suspend / resume / reset

conditions, and remote wakeup. It also autonomously handles the error conditions such as retry for CRC errors, Data

toggle errors, and generation of NYET, STALL, ACK and NACK depending on the endpoint buffer status.

During the power down state, the SIE clock is stopped. The SIE can asynchronously detect a USB Reset and/or

USB Resume condition and wakeup the 8051.

6.2.1

AUTONOMOUS USB PROTOCOL

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