USB97C201 datasheet(48/59 Pages) SMSC

48 / 59 page

SMSC DS – USB97C201

Page 48

Rev. 03/25/2002

PRELIMINARY

6.3.6.3

Cyclic Redundancy Checking (CRC) Calculation

Cyclic Redundancy Checking (CRC-16) is used for error checking on Ultra ATA/66 transfers. The CRC value is

calculated for all data by both the USB97C201 and the IDE device over the duration of the DMA burst transfer

segment. This segment is defined as all data transferred with a valid STROBE edge from DACK assertion to nDACK

deassertion. At the end of the transfer burst segment, the USB97C201 will drive the CRC value onto the D[15:0]

signals. The value is then latched by the IDE device on deassertion of nDACK. The IDE device compares the

USB97C201 CRC value to its own and reports an error if there is a mismatch.

6.4

SRAM Buffers

1.25K Bytes of Buffer SRAM are provided. The Memory Map of the buffers are given below:

Table 64 –Buffer SRAM Mapping

SRAM ADDRESS

BUFFER DESCRIPTION

0x300 – 0x4FF

SRAM B 512 byte EP2/ATA buffer

0x100 – 0x2FF

SRAM A 512 byte EP2/ATA buffer

0x0C0 – 0x0FF

64 Byte EP1 TX Buffer

0x080 – 0x0BF

64 Byte EP1 RX Buffer

0x040 – 0x07F

64 Byte EP0 TX Buffer

0x000 – 0x03F

64 Byte EP0 RX Buffer

Note: The above SRAM address in the table refers to the BYTE location within the SRAM. The SRAM is actually

physically organized as a 32 bit wide memory.

The buffers used for EP2 is organized as two 512 byte buffers: A and B. The A buffer has its address starting at

0X100, while the B is at address 0X300.. Byte counts for data received or to be transmitted is contained in the

RAMWRBC_A/B and RAMRDBC

_A/B register sets, respectively. The direction of data flow is determined by the DIR

bit in the EP2 Control register. If DIR=0 then data flow is from the SIE to SRAM and from the SRAM to the ATA

interface. If DIR=1 the data flow is in the opposite direction. Unlike EP0 and EP1, data for both directions can not be

simultaneously buffered in the SRAM for EP2. However, the dual buffers and automatic transfer operation (see

Section 6.9) allow for sustained 480Mbps transfers across the USB97C201.

6.5

8051 Options

The following 8051 core options are included:

256 SRAM in SFR space

Three timers

Single serial port

Extended external inputs (INT2-13)

External program memory and external data bus (XDATA) are pinned out as a common bus.

6.6

Address Multiplexing

Access to the SRAM for the three access points, ie SIE, ATA DMA, or 8051, is via a time division multiplexing

scheme (See Section 6.7). Each of the above blocks have access to read or write the SRAM during one of four sub-

periods (the fourth period being reserved for future expansion/idle) of a four phase 15 Mhz clock( ie 60 Mhz slice

clock). The values set in the EPx_BUFx , and IN_BUFx, or OUT_BUFx (depending on the direction set for EP2)

control the address counter for accesses by the EPs during their time-slice.

The IN_BUFx or OUT_BUFx (again,depending on the direction of EP2) controls the address for ATA access and

SRAM_ADDx does so for the 8051 accesses.

Which endpoint has access during the SIE’s time-slice is determined by the SIE, ie depending on what endpoint is

currently active on the USB bus. Since accesses occur at 15Mhz using DWORDs (32bits), this process is capable of

real time concurrency with the USB bus and does not require additional buffering in the SIE. Even if a received

packet is ultimately discarded, all that is required to do so is simply not generate the completion interrupt for that

endpoint. Similarly for the transmit process, allowing re-transmission.

USB97C201 Datasheet(PDF) 48 Page - SMSC Corporation

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