USB97C201 datasheet(51/59 Pages) SMSC

51 / 59 page

SMSC DS – USB97C201

Page 51

Rev. 03/25/2002

PRELIMINARY

RAMWR_A=0

RAMWR_B=0

RAMWR_

TOGGLE=0?

Yes

SRAM Data

Received?

Yes

RAMWR_A=1

RAMWR_B=0

RAMWR_

TOGGLE=1

RAMWR_A=0

RAMWR_B=1

RAMWR_

TOGGLE=0

SRAM Data

Received?

SRAM Data

Received?

Yes

RAMWR_A=1

RAMWR_B=1

(IN FLOW CONTROL

ACTIVE)

RAMWR_

TOGGLE=0?

Yes

SRAM Data

Received?

POR

A Buffer Output

Completed?

B Buffer Output

Completed?

Yes

CLEAR

RAMWR_A

CLR

RAMWR_B

A Buffer Output

Completed?

Yes

B Buffer Output

Completed?

CLR RAMWR_B;

Yes

RAMWR_TOGGLE=1;

(IN FLOW CONTROL

OFF)

CLR RAMWR_A;

CLR

RAMWR_TOGGLE;

(IN FLOW CONTROL OFF)

FIGURE 3 - RECEIVE BUFFER OPERATION

Trapezoidal shapes indicate actions performed by the firmware. The hardware state machine is responsible for

automatically changing the state of RAMWR_TOGGLE according to the state change of the RAMWR_B and

RAMWR_A bits, as shown in

Table 65. These bits are normally set by the USB97C201 upon completion of loading

the A or B SRAM buffer and are normally cleared by the firmware (except when Auto Transfer operation is enabled,

see Section 6.9.3).

Note that when both buffers are “full”, ie RAMWR_A and RAMWR_B status bits are BOTH set, that the

RAMWR_TOGGLE is not altered and that flow control is initiated on the input source. If this source is the SIE, it will

NYET or NAK further OUTs. If it is the ATA interface, nDAK will not be asserted in response to DRQ and data not

clocked in to the SRAM.

Table 65 – RAMWR_TOGGLE State Control

RAMWR_B

RAMWR_A

RAMWR_TOGGLE

COMMENT

0->1

A buffer filled; B buffer empty;

change to B buffer buffer

0->1

1->0

B buffer filled, A buffer empty;

change to A buffer buffer

0->1

No Change (0)

Both buffers filled; source flow

controlled.

0->1

No Change (1)

Both buffers filled; source flow

controlled

1->0

X->1

B buffer emptied; A buffer full;

change to A buffer buffer.

1->0

X->0

A buffer emptied; B buffer full;

change to A buffer buffer.

6.9.2

TRANSMIT BUFFER OPERATION

Figure 4 illustrates the operation of the transmit A and B buffers.

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