USB97C201 datasheet(41/59 Pages) SMSC

41 / 59 page

SMSC DS – USB97C201

Page 41

Rev. 03/25/2002

PRELIMINARY

IDE_TIM

(0xDF - RESET=0x00)

IDE TIMING REGISTER

BIT

NAME

R/W

DESCRIPTION

PPE

R/W

Prefetch and Posting Enable.

1:Prefetch and posting to the IDE data port is enabled for the

drive.

0: Prefetch and posting is disabled for the drive .

ISPE

R/W

IORDY Sample Point Enable.

1: All accesses to the ATA I/O address range sample IORDY.

The IORDY sample point is specified by the “IORDY Sample

Point” field of this register.

0: IORDY sampling is disabled. The internal IORDY signal is

forced asserted guaranteeing that IORDY is sampled asserted

at the first sample point as specified by the “IORDY Sample

Point” field in this register.

FTB

R/W

Fast Timing Bank.

1: Accesses to the data port of the ATA IO address range

uses fast timings. PIO accesses to the data port use fast

timing only if bit 3 of this register is zero. Accesses to all non-

data ports of the ATA I/O address range always use the 8 bit

compatible timings.

0: Accesses to the data port of the ATA I/O address range

uses the 16 bit compatible timing.

Note: the following settings should be used for the ISP, RT, DTE, and FTB bits for the various PIO and MWDMA

modes:

MODE

ISP[1:0]

RT[1:0]

FTB

DTE

COMMENT

PIO Mode 0

ATA PIO cycle speed limited by 8051 data moves

PIO Mode 1

ATA PIO cycle speed limited by 8051 data moves

PIO Mode 2-4

ATA PIO cycle speed limited by 8051 data moves

MWDMA 0

requires compatibility mode timing to be used

MWDMA 1

MWDMA 2

USB97C201 Datasheet(PDF) 41 Page - SMSC Corporation

USB97C201 Datasheet(HTML) 41 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Datasheet Download

Link URL