USB97C201 datasheet(24/59 Pages) SMSC

24 / 59 page

SMSC DS – USB97C201

Page 24

Rev. 03/25/2002

PRELIMINARY

Table 13 - GPIO Output Register

GPIO_OUT

(0x9A- RESET=0x00)

GPIO DATA OUTPUT

BIT

NAME

R/W

DESCRIPTION

GPIO7

R/W

GPIO7 Output Buffer Data

GPIO6

R/W

GPIO6 Output Buffer Data

GPIO5

R/W

GPIO5 Output Buffer Data

GPIO4/nWE

R/W

GPIO4 Output Buffer Data

GPIO3/T1

R/W

GPIO3 Output Buffer Data

GPIO2/T0

R/W

GPIO2 Output Buffer Data

GPIO1/TXD

R/W

GPIO1 Output Buffer Data

GPIO0/RXD

R/W

GPIO0 Output Buffer Data

Table 14 - GPIO Input Register

GPIO_IN

(0x9B- RESET=0x00)

GPIO INPUT REGISTER

BIT

NAME

R/W

DESCRIPTION

GPIO7

GPIO7 Input Buffer Data

GPIO6

GPIO6 Input Buffer Data

GPIO5

GPIO5 Input Buffer Data

GPIO4/nWE

GPIO4 Input Buffer Data

GPIO3/T1

GPIO3 Input Buffer Data

GPIO2/T0

GPIO2 Input Buffer Data

GPIO1/TXD

GPIO1 Input Buffer Data

GPIO0/RXD

GPIO0 Input Buffer Data

Table 15 – GPIO Interrupt Status Register (INT4)

GPIO_IRQ

(0XC0- RESET=0x00)

GPIO INTERRUPT STATUS REGISTER

BIT

NAME

R/W

DESCRIPTION

GPIO7_IRQ

R/W

1 = A level change has occurred on GPIO7.

GPIO6_IRQ

R/W

1 = A level change has occurred on GPIO6.

GPIO5_IRQ

R/W

1 = A level change has occurred on GPIO5.

GPIO4_IRQ

R/W

1 = A level change has occurred on GPIO4.

GPIO3_IRQ

R/W

1 = A level change has occurred on GPIO3.

GPIO2_IRQ

R/W

1 = A level change has occurred on GPIO2.

GPIO1_IRQ

R/W

1 = A level change has occurred on GPIO1.

GPIO0_IRQ

R/W

1 = A level change has occurred on GPIO0.

Note 1: Writing a “1” (one) to a bit clears the bit and enables the detection of the next level transition. If not masked

by the corresponding bit in the GPIO_MSK register, “1” in any bit in this register will force a “1” on the 8051

core’s external INT4 interrupt input.

USB97C201 Datasheet(PDF) 24 Page - SMSC Corporation

USB97C201 Datasheet(HTML) 24 Page - SMSC Corporation

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