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IP175G Datasheet(PDF) 10 Page - List of Unclassifed Manufacturers

Part # IP175G
Description  5 Port 10/100 Ethernet Integrated Switch
PDF  69 Pages
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Manufacturer  ETC2 [List of Unclassifed Manufacturers]
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IP175G Datasheet(HTML) 10 Page - List of Unclassifed Manufacturers

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IP175G/GI/GH/GHI
Data Sheet
10 / 69
November 27, 2012
Copyright © 2012, IC Plus Corp.
IP175Gx-DS-R01.3
3.3 System clock & reset pins
Pin
No.
Label
Type
Description
23
OSCI
I
25MHz system clock
It is recommended to connect OSCI and X2 to a 25MHz crystal.
If the clock source is from another chip or oscillator, the clock
should be active at least for 1ms before pin 25 RESETB
de-asserted.
Pin 24 X2 should be left open in this application.
24
X2
O
Crystal pin
A 25Mhz crystal can be connected to OSCI and X2.
25
RESETB
I
Reset
It is a low active input pad with Schmitt trigger. The reset time
must be hold for more than 10 ms. If an R/C reset circuit is used,
the capacitor should be connected to PVDD as shown in the
figure.
3.4 Boundry scan & test mode
Pin
No.
Label
Type
Description
29
TEST
I
Test mode enable
It should be connected to GND for normal operation
30
AUTO_FACTORY
_TEST
IPL
Auto Factory Test (AFT
®) enable pin
RESETB
R
PVDD
C



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