IP175G/GI/GH/GHI

Data Sheet

3 / 69

November 27, 2012

Copyright © 2012, IC Plus Corp.

IP175Gx-DS-R01.3

5.1

Register map...........................................................................................................................28

5.1.1

MII register map ............................................................................................................28

6

PHY registers.......................................................................................................................................................... 29

6.1

MII Register .............................................................................................................................30

6.2

MMD Control Register.............................................................................................................37

6.3

MMD Data Register.................................................................................................................37

6.4

LED mode Control Register ....................................................................................................41

6.5

Register Page mode Control Register ....................................................................................42

6.6

WOL+ Control Register ...........................................................................................................42

6.7

Switch control registers (I).......................................................................................................44

6.8

Test mode control registers .....................................................................................................45

6.9

Port mirroring control registers................................................................................................46

6.10 Debug Register .......................................................................................................................46

6.11 Fiber duplex setting registers ..................................................................................................47

6.12 Backpressure setting registers................................................................................................48

6.13 TCP/UDP port priority registers...............................................................................................48

6.14 Test mode................................................................................................................................49

6.15 CoS control registers – port 0 .................................................................................................49

6.16 CoS control registers – port 1 .................................................................................................49

6.17 CoS control registers – port 2 .................................................................................................49

6.18 CoS control registers – port 3 .................................................................................................50

6.19 CoS control registers – port 4 .................................................................................................50

6.20 Switch control registers (IV) ....................................................................................................50

6.21 Reserved Group MAC addresses ...........................................................................................52

6.22 Switch control registers (II)......................................................................................................56

6.23 EEE Timing Parameter............................................................................................................57

6.24 WOL (Wake on LAN)...............................................................................................................58

6.25 Link Aggregation .....................................................................................................................58

6.26 VLAN Group Control Register.................................................................................................59

6.26.1 VLAN Classification ......................................................................................................59

6.26.2 VLAN Ingress Rule .......................................................................................................59

6.26.3 Default VLAN Information .............................................................................................60

6.26.4 VLAN TAG Control Register..........................................................................................60

6.26.5 Port Based VLAN Member Register .............................................................................61

6.26.6 Leaky VLAN Control Register .......................................................................................61

6.27 VLAN Table .............................................................................................................................61

6.27.1 VLAN Control Register..................................................................................................61

6.27.2 VLAN Identifier Register ...............................................................................................61

6.27.3 VLAN Member Register ................................................................................................62

7

Electrical Characteristics ........................................................................................................................................ 64

7.1

Absolute Maximum Rating ......................................................................................................64

7.2

DC Characteristic ....................................................................................................................64

7.3

AC Timing................................................................................................................................65

7.3.1

Power On Sequence and Reset Timing........................................................................65

8

Crystal Specifications.............................................................................................................................................. 65

8.1.1

EEPROM Timing ...........................................................................................................67

8.1.1.1

Data read cycle ...................................................................................................67

8.1.1.2

Command cycle ..................................................................................................67

8.2

Thermal Data...........................................................................................................................67

9

Order Information.................................................................................................................................................... 68

10 Package Detail........................................................................................................................................................ 69

10.1 48 QFN Outline Dimensions ...................................................................................................69