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RF68

4.2. Mode Selection Flowchart

Circuit Start-up

Wait T_Start

Logic ‘0’

Check

CTRL Pin

Logic ‘1’

Power & Go 1

868.3 MHz

FSK, Fdev=+/-19.2kHz

+10dBm

Power & Go 2

433.92 MHz

OOK

+10dBm

CTRL Clock signal

Advanced Mode Full

register flexibility Automatic

or forced Transmit

Figure 4. RF68 Mode Selection

Note

Advanced mode is entered only if DATA is held low during CTRL’s rising edge.

When powering up the circuit (microcontroller and RF68), the logic level of the CTRL pin is sampled after T_START, as

described on Figure 5. During T_START, the microcontroller IO driving the CTRL pin must be configured as an output,

driving the CTRL pin to the desired state.

Figure 5. Power-up Timing