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AD7380 Datasheet(PDF) 16 Page - Analog Devices

Part # AD7380
Description  Dual, Simultaneous Sampling SAR ADCs, Differential Inputs
PDF  31 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7380 Datasheet(HTML) 16 Page - Analog Devices

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AD7380/AD7381
Data Sheet
Rev. 0 | Page 16 of 31
APPLICATIONS INFORMATION
Figure 31 shows an example of a typical application circuit for
the AD7380/AD7381. Decouple the VCC, VLOGIC, REGCAP, and
REFIO pins with suitable decoupling capacitors as shown.
The exposed pad is a ground reference point for circuitry on the
device and must be connected to the board ground.
A differential resistor capacitor (RC) filter must be placed on
the analog inputs to ensure performance is achieved.
The performance of the AD7380/AD7381 device may be
impacted by noise on the digital interface. This impact is
dependent on board layout and design. Keep a minimal
distance of the digital line to the digital interface or place a
100 Ω resistor in series and close to the SDOA pin and
SDOB pin to reduce noise from the digital interface coupling of
the AD7380/AD7381.
POWER SUPPLY
The AD7380/AD7381 have two independent power supplies,
VCC and VLOGIC, that supply the analog circuitry and digital
interface, respectively. Decouple both the VCC supply and the
VLOGIC supply separately with a 1 µF capacitor. Additionally,
there is an internal low dropout (LDO) regulator that supplies the
AD7380/AD7381. The on-chip regulator provides a 1.9 V
supply for internal use on the devices only. Decouple the
REGCAP pin with a 1 µF capacitor to GND.
Power-Up
The AD7380/AD7381 are robust to power supply sequencing.
VCC and VLOGIC can be applied in any sequence. An external
reference must be applied after VCC and VLOGIC are applied.
The AD7380/AD7381 require a tPOWERUP time from applying VCC
and VLOGIC until the ADC conversion results are stable.
Applying CS pulses or interfacing with the AD7380/AD7381
prior to the setup time elapsing does not have a negative impact
on ADC operation. Conversion results are not guaranteed to
meet data sheet specifications during this time, however, and
must be ignored.
AINA+
AINA–
AINB+
AINB–
VCC
VLOGIC
SDOB
SDOA
SDI
SCLK
CS
GND
GND
REFIO
3.3V
3.3V
1µF
1µF
3
3Ω
3
3Ω
330pF
68pF
68pF
330pF
68pF
68pF
3
3Ω
3
3Ω
REGCAP
1µF
EXPOSED
PAD
1µF
REF
100Ω
100Ω
AD7380/AD7381
Figure 31. Typical Application Circuit



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