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AD7380/AD7381

Data Sheet

Rev. 0 | Page 18 of 31

Rolling Average Oversampling

Rolling oversampling mode can be used in applications where

higher output data rates are required and where higher SNR or

dynamic range is desirable. Rolling averaging involves taking a

number of samples, adding the samples together, and dividing

the result by the number of samples taken. This result is then

output from the device. The sample data is not cleared after the

process is completed. The rolling oversampling mode uses a

first in, first out (FIFO) buffer of the most recent samples in the

averaging calculation, allowing the ADC throughput rate and

output data rate to stay the same.

Rolling oversampling mode is configured by setting the

OS_MODE bit to Logic 1 and having a valid nonzero value in

the OSR[2:0] bits. The oversampling ratio of the digital filter is

controlled using the oversampling bits, OSR[2:0] (see Table 10).

The output result is decimated to 16-bit resolution for the AD7380

and a 14-bit result for the AD7381. If additional resolution is

required, this resolution can be achieved by configuring the

resolution boost bit in the CONFIGURATION1 register. See the

Resolution Boost section for further details.

In rolling average oversampling mode, all ADC conversions are

controlled and initiated by the falling edge of CS. After a

conversion is complete, the result is loaded into the FIFO. The

FIFO length is 8, regardless of the oversampling ratio set. The

FIFO is filled on the first conversion after a power-on reset, the

first conversion after a software controlled hard or soft reset, or

the first conversion after the REFSEL bit is toggled. A new

conversion result is shifted into the FIFO on completion of

every ADC conversion, regardless of the status of the OSR[2:0] bits

and the OS_MODE bit. This conversion allows a seamless

transition from no oversampling to rolling average

oversampling, or different rolling average oversampling ratios

without waiting for the FIFO to fill.

The number of samples, n, defined by the OSR[2:0] bits are

taken from the FIFO, added together, and the result is divided

by n. The time between CS falling edges is the cycle time which

can be controlled by the user, depending on the desired data

output rate.

Table 10. AD7380/AD7381 Rolling Averaging Oversampling Performance Overview

Oversampling

Ratio

AD7380

AD7381

SNR (dB typical)

Output Data Rate (kSPS

maximum)

SNR (dB typical)

Output Data Rate (kSPS

maximum)

VREF = 2.5 V

VREF = 3.3 V

RES = 0

RES = 1

RES = 0

RES = 1

RES = 0

RES = 1

Disabled

92.5

4000

93.2

94.5

4000

84.5

87.7

4000

94.8

97.2

4000

95.5

98.6

95.9

99.6

4000

85.5

4000

INTERNAL

VDD

SDI

SDOA

SDOB

ACQ

ENABLE OS = 2

ENABLE OS = 4

DON’T CARE

ACQ

...

FIFO

–

FIFO

–

FIFO

–

FIFO

–

FIFO

–

FIFO

–

FIFO

–

(FIFO1 + FIFO2 +

FIFO3 + FIFO4)/4

(FIFO1 +

FIFO2)/2

(FIFO1 +

FIFO2)/2

(FIFO1 +

FIFO2)/2

Figure 33. Rolling Average Oversampling Operation

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