AD7380 datasheet(21/31 Pages) AD

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Data Sheet

AD7380/AD7381

Rev. 0 | Page 21 of 31

INTERFACE

The interface to the AD7380/AD7381 is via a serial interface.

The interface consists of a CS, SCLK, SDOA, SDOB, and SDI pins.

The CS signal frames a serial data transfer and initiates an ADC

conversion process. The falling edge of CS puts the track-and-

hold into hold mode, at which point the analog input is sampled,

and the bus is taken out of three-state.

The SCLK signal synchronizes data in and out of the device via

the SDOA, SDOB, and SDI signals. A minimum of 16 SCLKs

are required for a write to or read from a register. The minimum

numbers of SCLKs for a conversion read is dependent on the

resolution of the device and the configuration settings, see

Table 11.

The ADC conversion operation is driven internally by an on-

board oscillator and is independent of the SCLK signal.

The AD7380/AD7381 have two serial output signals, SDOA

and SDOB. To achieve the highest throughput of the device, use

both SDOA and SDOB, 2-wire mode, to read the conversion

results. If a reduced throughput is required or oversampling is

used, it is possible to use 1-wire mode, SDOA signal only, for

reading conversion results. Programming the SDO bit in the

CONFIGURATION2 register configures 2-wire or 1-wire mode.

Configuring the cyclic redundancy check (CRC) operation for

SPI reads or SPI writes alters the operation of the interface. The

relevant sections of this data sheet must be consulted to ensure

correct operation.

READING CONVERSION RESULTS

The CS signal initiates the conversion process. A high to low

transition on the CS signal initiates a simultaneous conversion

of both ADCs, ADC A and ADC B. The AD7380/AD7381 have

a one cycle readback latency. Therefore, the conversion results

are available on the next SPI access. Then, take the CS signal

low, and the conversion result clocks out on the serial output

pins. The next conversion is also initiated at this point.

The conversion result is shifted out of the device as a 16-bit

result for the AD7380 and a 14-bit result for the AD7381. The

MSB of the conversion result is shifted out on the CS falling

edge. The remaining data is shifted out of the device under the

control of the SCLK input. The data is shifted out on the rising

edge of the SCLK, and the data bits are valid on both the falling

edge and the rising edge. After the final SCLK falling edge, take CS

high again to return the SDOx pins to a high impedance state.

The number of SCLK cycles to propagate the conversion results

on the SDOx pins is dependent on the serial mode of operation

configured and if resolution boost mode is enabled, see Figure 36

and Table 11 for details. If CRC reading is enabled, this requires

additional SCLK pulses to propagate the CRC information, see

the CRC section for more details.

As the CS signal initiates a conversion, as well as framing the

data, any data access must be completed within a single frame.

123

n–2

n–1

SDOx

SCLK

CONVERSION RESULT

1CONSULT TABLE 11 FOR n, THE NUMBER OF SCLK PULSES REQUIRED

Figure 36. Reading Conversion Result

Table 11. Number of SCLKs, n, Required for Reading Conversion Results

Interface Configuration

Resolution Boost Mode

CRC Read

AD7380

AD7381

2-Wire

Disabled

Enabled

Disabled

Enabled

1-Wire

Disabled

Enabled

Disabled

Enabled

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