AD7380 datasheet(17/31 Pages) AD

17 / 31 page

Data Sheet

AD7380/AD7381

Rev. 0 | Page 17 of 31

MODES OF OPERATION

The AD7380/AD7381 have several on-chip configuration

registers for controlling the operational mode of the device.

OVERSAMPLING

Oversampling is a common method used in analog electronics

to improve the accuracy of the ADC result. Multiple samples of

the analog input are captured and averaged to reduce the noise

component from quantization noise and thermal noise (kTC) of

the ADC. The AD7380/AD7381 offer an oversampling function

on-chip and have two user configurable oversampling modes,

normal averaging and rolling average.

The oversampling functionality is configured by

programming the OS_MODE bit and OSR[2:0] bits in the

CONFIGURATION1 register.

Normal Averaging Oversampling

Normal oversampling mode can be used in applications where

slower output data rates are allowable and where higher SNR or

dynamic range is desirable. Normal averaging involves taking a

number of samples, adding the samples together, and dividing

the result by the number of samples taken. This result is then

output from the device. The sample data is cleared after the

process is completed.

Normal oversampling mode is configured by setting the

OS_MODE bit to Logic 0 and having a valid nonzero value in

the OSR[2:0] bits. Writing to the OSR[2:0] bits has a two cycle

latency before the register gets updated. The oversampling ratio

of the digital filter is controlled using the oversampling bits,

OSR[2:0], which provides the oversampling bit decoding to

select the different oversample rates. The output result is

decimated to 16-bit resolution for the AD7380 and a 14-bit

resolution for the AD7381. If additional resolution is required,

this can be achieved by configuring the resolution boost bit in

the CONFIGURATION1 register. See the Resolution Boost

section for further details.

The number of samples, n, defined by the OSR[2:0] bits are

taken, added together, and the result is divided by n. The initial

ADC conversion is initiated by the falling edge of CS, and the

AD7380/AD7381 control all subsequent samples in the

oversampling sequence internally. The sampling rate of the

additional n samples is at 3 MSPS for the AD7380 and 4 MSPS

for AD7381 in oversampling mode. The oversampled

conversion result is ready for read back on the next serial interface

access. After the technique is applied, the sample data used in

the calculation is discarded. This process is repeated every time

the application needs a new conversion result and initiates by

the falling edge of CS.

As the output data rate is reduced by the oversampling ratio,

the SPI SCLK frequency required to transmit the data is also

reduced accordingly.

Table 9. AD7380/AD7381 Normal Averaging Oversampling Performance Overview

Oversampling

Ratio

AD7380

AD7381

SNR (dB typical)

Output Data Rate

(kSPS maximum)

SNR (dB typical)

Output Data Rate

(kSPS maximum)

VREF = 2.5 V

VREF = 3.3 V

RES = 0

RES = 1

RES = 0

RES = 1

RES = 0

RES = 1

Disabled

90.8

92.5

3000

85.2

4000

92.6

93.6

94.0

95.5

1500

84.7

2000

94.3

96.5

95.4

98.2

750

85.2

91.1

1000

95.8

99.2

96.3

100.5

375

85.5

500

96.3

100.4

96.8

102.0

187.5

85.7

94.6

250

96.5

100.5

97.0

102.8

93.75

85.9

95.6

125

SDOB

SDOA

INTERNAL

ACQ

DON’T CARE

t0 RESULT

ACQ

DON’T CARE

CONVERT START AT

t0 RESULT

Figure 32. Normal Averaging Oversampling Operation

AD7380 Datasheet(PDF) 17 Page - Analog Devices

AD7380 Datasheet(HTML) 17 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Datasheet Download

Link URL