AD5940 datasheet(32/130 Pages) AD

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AD5940

Data Sheet

Rev. 0 | Page 32 of 130

Bits

Bit Name

Settings

Description

Reset

Access

[11:0]

DACIN12

Low power DAC 12-bit output data register (1 LSB = 537 µV). A value between 0 and

0xFFF sets the 12-bit output voltage.

0x0

R/W

Sets output voltage to 0.2 V.

0xFFF

Sets output voltage to 2.4 V.

Low Power Reference Control Register—LPREFBUFCON

Address 0x00002050, Reset: 0x00000000, Name: LPREFBUFCON

Table 18. Bit Descriptions for LPREFBUFCON Register

Bits

Bit Name

Settings

Description

Reset

Access

[31:2]

Reserved

Reserved.

0x0

LPBUF2P5DIS

Low power output band gap buffer. This bit is normally cleared to enable the

low power reference buffer.

0x0

R/W

Enables the low power 2.5 V buffer.

Powers down the low power 2.5 V buffer.

LPREFDIS

Low power band gap power-down bit. This bit is normally cleared to enable the

low power reference.

0x0

R/W

Low power reference enabled.

Low power reference powered down.

Common-Mode Switch Mux Register—SWMUX

Address 0x0000235C, Reset: 0x00000000, Name: SWMUX

Table 19. Bit Descriptions for SWMUX Register

Bits

Bit Name

Settings

Description

Reset

Access

[31:4]

Reserved

Reserved.

0x0

CMMUX

Common-mode resistor select for AIN2 pin and AIN3 pin.

0x0

R/W

Common-mode switch off.

Enables the common-mode switches with a 10 MΩ resistor to set up the common-mode

voltage on the AIN2 and AIN3 pins. The voltage is driven by the low power TIA and the

AIN4/LPF0 pin.

[2:0]

Reserved

Reserved.

0x0

R/W

AD5940 Datasheet(PDF) 32 Page - Analog Devices

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