68HC705JB3 datasheet(129/134 Pages) FREESCALE

129 / 134 page

November 5, 1998

GENERAL RELEASE SPECIFICATION

MC68HC05JB3

MOTOROLA

REV 1

A-3

A.4

BOOTSTRAP MODE

Bootloader mode is entered upon the rising edge of RESET if the IRQ/VPP pin is

at VTST and the PB0 pin is at logic zero. The Bootloader program is masked in the

ROM area from $1E00 to $1FEF. This program handles copying of user code from

an external EPROM into the on-chip EPROM. The bootload function has to be

done from an external EPROM. The bootloader performs one programming pass

at 1ms per byte then does a verify pass.

The user code must be a one-to-one correspondence with the internal EPROM

addresses.

A.5

EPROM PROGRAMMING

Programming the on-chip EPROM is achieved by using the Program Control Reg-

ister located at address $3E.

Please contact Motorola for programming board availability.

A.5.1 EPROM Program Control Register (PCR)

This register is provided for programming the on-chip EPROM in the

MC68HC705JB3.

MORON – Mask Option Register ON

0 =

Disable programming to Mask Option Register ($01FF)

1 =

Enable programming to Mask Option Register ($01FF)

ELAT – EPROM LATch control

0 =

EPROM address and data bus conﬁgured for normal reads

1 =

EPROM address and data bus conﬁgured for programming (writes

to EPROM cause address and data to be latched). EPROM is in

programming mode and cannot be read if ELAT is 1. This bit should

not be set when no programming voltage is applied to the Vpp pin.

PGM – EPROM ProGraM command

0 =

Programming power is switched OFF from EPROM array.

1 =

Programming power is switched ON to EPROM array. If ELAT

≠1,

then PGM=0.

Bits [7:3] – Reserved

These are reserved bits and should remain zero.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

PCR

00000

MORON

ELAT

PGM

$003E

reset:

00000000

= Reserved

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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