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AD7739

Rev. 0 | Page 5 of 32

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER REQUIREMENTS

AVDD to AGND Voltage

4.75

5.25

DVDD to DGND Voltage

4.75

5.25

2.70

3.60

AVDD Current (Normal Mode)

13.6

AVDD Current (Reduced Power Mode)

9.2

MCLK = 4 MHz

AVDD Current (Internal Buffer Off)

8.5

DVDD Current (Normal Mode) 13

2.7

DVDD = 5 V

DVDD Current (Normal Mode) 13

1.0

1.5

DVDD = 3 V

Power Dissipation (Normal Mode) 13

100

Power Dissipation

(Reduced Power Mode)13

DVDD = 5 V, MCLK = 4 MHz

Power Dissipation

(Reduced Power Mode)13

DVDD = 3 V, MCLK = 4 MHz

AVDD + DVDD Current

(Standby Mode)14

µA

Power Dissipation (Standby Mode)14

500

µW

1 Specification is not production tested, but is supported by characterization data at initial product release.

2 See Typical Performance Characteristics.

3 Specifications before calibration. Channel system calibration reduces these errors to the order of the noise.

4 Applies after the zero-scale and full-scale calibration. The negative full-scale error represents the remaining error after removing the offset and gain error.

5 Specifications before calibration. ADC zero-scale self-calibration or channel zero-scale system calibration reduce this error to the order of the noise.

6 For specified performance. The output data span corresponds to the specified nominal input voltage range. The ADC is functional outside the nominal input voltage

range, but the performance might degrade. Outside the nominal input voltage range, the OVR bit in the channel status register is set and the channel data register

value depends on the CLAMP bit in the mode register. See the register and circuit descriptions for details.

7 For specified performance. If the analog input absolute voltage (referred to AGND) changes more than 0.5 V during one conversion time, the result could be affected

by distortion in the input buffer. This limit does not apply to analog input absolute voltages below 3 V.

8 If chopping is enabled or when switching between channels, a dynamic current charges the capacitance of the multiplexer. See the circuit description for details.

9 For specified performance. Part is functional with lower VREF.

10 Dynamic current charging the sigma-delta modulator input switching capacitor.

11 Outside the specified calibration range, calibration is possible but the performance may degrade.

12 These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load.

13 With external MCLK, MCLKOUT disabled (CLKDIS bit set in the mode register

14 External MCLKIN = 0 V or DVDD, digital inputs = 0 V or DVDD, P0 and P1 = 0 V or AVDD.

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