AD7739

Rev. 0 | Page 19 of 32

CHANNEL SETUP REGISTERS

8 Bits, Read/Write Registers, Address 0x28–0x2F, Default Value 0x00

These registers are used to configure the selected channel, to configure its input voltage range, and to set up the corresponding channel

status register.

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Mnemonic

BUFOFF

COM1

COM0

Stat OPT

ENABLE

RNG2

RNG1

RNG0

Default

0

0

0

0

0

0

0

0

Bit

Mnemonic

Description

7

BUFOFF

Buffer Off. If reset to 0, then the internal buffer is enabled.

Operation only with the internal buffer enabled is recommended.

6–5

COM1, COM0

Analog inputs configuration:

COM1

COM0

COM1

COM0

Channel

0

0

1

1

0

AIN0–AINCOM

AIN0–AIN1

1

AIN1–AINCOM

AIN2–AIN3

2

AIN2–AINCOM

AIN4–AIN5

3

AIN3–AINCOM

AIN6–AIN7

4

AIN4–AINCOM

AIN0–AIN1

5

AIN5–AINCOM

AIN2–AIN3

6

AIN6–AINCOM

AIN4–AIN5

7

AIN7–AINCOM

AIN6–AIN7

4

Stat OPT

Status Option. When this bit is set to 1, the P0 and P1 bits in the channel status register will reflect the state of

the P0 and P1 pins. When this bit is reset to 0, the RDY bit in the channel status register will reflect the channel

corresponding to the RDY bit in the ADC status register.

3

ENABLE

Channel Enable. Set this bit to 1 to enable the channel in the continuous conversion mode. A single

conversion will take place regardless of this bit’s value.

2–0

RNG2–RNG0

This is the channel input voltage range:

RNG2

RNG1

RNG0

Nominal Input Voltage Range

1

0

0

±2.5 V

1

0

1

+2.5 V

0

0

0

±1.25 V

0

0

1

+1.25 V

0

1

0

±0.625 V

0

1

1

+0.625 V