THS4541 datasheet(28/64 Pages) TI1

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Vod

Vocm

Vocm G1

Vicm G1

Vod

THS4541-Q1

SLOS930B – NOVEMBER 2015 – REVISED NOVEMBER 2019

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8.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances

The THS4541-Q1 offers a trimmed input offset voltage and extremely low offset drift over the full –40°C to

+125°C operating range. This offset voltage combines with several other error contribution terms to produce an

initial 25°C differential offset error band, and then a drift over temperature. For each error term, a gain must be

assigned to that term. For this analysis, only DC-coupled signal paths are considered. One new source of output

error (versus typical op amp analysis) arises from the effect that mismatched resistor values and ratios can have

on the two sides of the FDA. Any common-mode voltage or drift creates a differential output error through the

slight mismatches arising from the external feedback and gain-setting resistor tolerances, and the approximation

(or snap) to standard value.

The error terms (25°C and drift), along with the gain to the output differential voltage, include:

•

Input offset voltage—this voltage has a gain equal to the noise gain or 1 + Rf / Rg, where Rg is the total DC

impedance from the input pins back to the source, or a DC reference (typically ground).

•

Input offset current—this current has a gain to the differential output through the average feedback resistor

value.

The remaining terms arise from an assumed range on both the absolute feedback resistor mismatch and the

mismatch in the divider ratio on each side of the FDA. The first of these resistor mismatch terms is the input bias

current creating a differential output offset because of Rf mismatch. For simplicity, the upper Rf and Rg values

are called Rf1 and Rg1 with a ratio of Rf1 / Rg1

≡ G1. The lower elements are defined as Rf2 and Rg2 with a

ratio of Rf2 / Rg2

≡ G2. To compute worst-case contributions, a maximum variation in the design resistor

tolerance is used in the absolute and ratio mismatches. For instance, ±1% tolerance resistors are assumed,

giving a worst-case G1 that is 2% higher than nominal and a G2 that is 2% lower than nominal, with a worst-case

Rf value mismatch of 2% as well. For matched impedance designs with Rt and Rg1 on a single-ended to

differential stage, the standard value snap imposes a fixed mismatch in the initial feedback ratios with the resistor

tolerance adding a mismatch to this initial ratio mismatch. Define the selected external resistor tolerance as ±T

(so for 1% tolerance resistors, T = 0.01).

•

Total gain for bias current error is ±2 × T × Rfnom

Anything that generates an output common-mode level or shift over temperature also generates an output

differential error term if the two feedback ratios, G1 and G2, are not equal. An error trying to produce a shift in

the output common-mode is overridden by the common-mode control loop, where any feedback ratio mismatch

creates a balanced, differential error around the Vocm output.

The terms that create a differential error from a common-mode term and feedback ratio mismatch include the

desired Vocm voltage, any source common-mode voltage, any drift on the reference bias to the Vocm control

pin, and any internal offset and drift in the Vocm control path.

Considering just the output common-mode control and the source common-mode voltage (Vicm), the conversion

to output differential offsets is done by using Equation 4:

(4)

Neglecting any G1 and G2 mismatch because of standard values snap, the conversion gain for these two terms

can be recast in terms of the nominal Rf / Rg

≡ G, and tolerance T, as shown in Equation 5. As G increases, this

conversion gain approaches 4T, as a worst-case gain for these terms to output differential offset.

(5)

THS4541 Datasheet(PDF) 28 Page - Texas Instruments

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