CS5461A datasheet(21/41 Pages) CIRRUS

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CS5461A

DS661F1

5.11 Event Handler

The INT pin is used to indicate that an internal error or

event has taken place in the CS5461A. Writing a logic 1

to any bit in the Mask Register allows the corresponding

bit in the Status Register to activate the INT pin. The in-

terrupt condition is cleared by writing a logic 1 to the bit

that has been set in the Status Register.

The behavior of the INT pin is controlled by the IMODE

and IINV bits of the Configuration Register.

If the interrupt output signal format is set for either falling

or rising edge, the duration of the INT pulse will be at

least one DCLK cycle (DCLK = MCLK/K).

5.11.1 Typical Interrupt Handler

The steps below show how interrupts can be handled.

INITIALIZATION:

1) All Status bits are cleared by writing 0xFFFFFF to

the Status Register.

2) The condition bits which will be used to generate

interrupts are then set to logic 1 in the Mask Reg-

ister.

3) Enable interrupts.

INTERRUPT HANDLER ROUTINE:

4) Read the Status Register.

5) Disable all interrupts.

6) Branch to the proper interrupt service routine.

7) Clear the Status Register by writing back the read

value in step 4.

8) Re-enable interrupts.

9) Return from interrupt service routine.

This handshaking procedure ensures that any new in-

terrupts activated between steps 4 and 7 are not lost

(cleared) by step 7.

5.12 Serial Port Overview

The CS5461A incorporates a serial port transmit and re-

ceive buffer with a command decoder that interprets

one-byte (8 bits) commands as they are received. There

are four types of commands; instructions, synchroniz-

ing, register writes and register reads (See Section 5.13

Commands on page 22).

Instructions are one byte in length and will interrupt any

instruction currently executing. Instructions do not affect

Synchronizing commands are one byte in length and

only affect the serial interface. Synchronizing com-

mands do not affect operations currently in progress.

Commands and data are transferred most-significant bit

(MSB) first. Figure 1 on page 11, defines the serial port

timing and required sequence necessary to write to and

read from the serial port receive and transmit buffer, re-

spectively. While reading data from the serial port, com-

mands and data can be simultaneously written. Starting

a new register read command while data is being read

will terminate the current read in progress. This is ac-

ceptable if the remainder of the current read data is not

needed. During data reads, the serial port requires input

data. If a new command and data is not sent, SYNC0 or

SYNC1 must be sent.

5.12.1 Serial Port Interface

The serial port interface is a “4-wire” synchronous serial

communications interface. The interface is enabled to

start excepting SCLKs when CS (Chip Select) is assert-

ed. SCLK (Serial bit-clock) is a Schmitt-trigger input that

is used to strobe the data on SDI (Serial Data In) into the

receive buffer and out of the transmit buffer onto SDO

(Serial Data Out).

If the serial port interface becomes unsynchronized with

respect to the SCLK input, any attempt to clock valid

commands into the serial interface may result in unex-

pected operation. The serial port interface must then be

re-initialized by one of the following actions:

Drive the CS pin high, then low.

Hardware Reset (drive RESET pin low, for at

least 10 µs).

Issue the Serial Port Initialization Sequence,

which is 3 (or more) SYNC1 command bytes

(0xFF) followed by one SYNC0 command byte

(0xFE).

If a resynchronization is necessary, it is best to re-initial-

ize the part either by hardware or software reset (0x80),

as the state of the part may be unknown.

IMODE

IINV

INT Pin

Active-low Level

Active-high Level

Low Pulse

High Pulse

Table 3. Interrupt Configuration

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