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PR533 Datasheet(PDF) 17 Page - NXP Semiconductors

Part # PR533
Description  USB NFC integrated reader solution
PDF  36 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PR533 Datasheet(HTML) 17 Page - NXP Semiconductors

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PR533_SDS
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product short data sheet
COMPANY PUBLIC
Rev. 3.6 — 27 October 2014
206436
17 of 36
NXP Semiconductors
PR533
USB NFC integrated reader solution
10.11 Input/output pin characteristics for DP and DM
[1]
The value does not guarantee the power-down consumptions. To reach the specified power-down consumptions, the limit is 0.4 V.
[2]
The IOH and IOL give the output driving capability and allow to calculate directly the rise and fall time as function of the load capacitance.
Table 18.
Input/output pin characteristics for DP and DM for USB interface
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIH
HIGH-level input voltage
VDD(PVDD) =3.3 V
2
-
3.6
V
VIL
LOW-level input voltage
[1] 0-
0.8
V
VOH
HIGH-level output voltage
VDD(PVDD) =3.3 V;
RPD =1.5  to VSS
2.8
-
VDD(PVDD) V
VOL
LOW-level output voltage
VDD(PVDD) =3.3 V;
RPD =1.5  to VDD(PVDD)
0-
0.3
V
IOH
HIGH-level output current
VDD(PVDD) =3.3 V;
VOH =0.8  VDD(PVDD)
[2]
4-
-
mA
VDD(PVDD) =1.8 V;
VOH =0.7  VDD(PVDD)
2-
-
mA
IOL
LOW-level output current
VDD(PVDD) =3.3 V;
VOL =0.2  VDD(PVDD)
[2] 4-
-
mA
VDD(PVDD) =1.8 V;
VOL =0.3  VDD(PVDD)
2-
-
mA
IIH
HIGH-level input current
VI =VDD(PVDD)
--1
A
IIL
LOW-level input current
VI = 0 V
--1
A
ILI
input leakage current
RSTPD_N = 0 V
1-
+1
A
Ci
input capacitance
-
2.5
3.5
pF
ZINP
input impedance exclusive of
pull-up/pull-down (for low-/full
speed)
300
-
-
k
ZDRV
driver output impedance for driver
which is not high-speed capable
28
-
44
tFDRATE
full-speed data rate for devices
which are not high-speed capable
11.97
-
12.03
Mb/s
tDJ1
source jitter total (including fre-
quency tolerance) to next transition
3.5
-
+3.5
ns
tDJ2
source jitter total (including fre-
quency tolerance) for paired transi-
tions
4-
+4
ns
tFDEOP
source jitter for differential transition
to SE0 transition
2-
+5
ns
tJR1
receiver jitter to next transition
18.5
-
+18.5
ns
tJR2
receiver jitter for paired transitions
9-
+9
ns
tFEOPT
source SE0 interval of EOP
160
-
175
ns
tFEOPR
receiver SE0 interval of EOP
82
-
-
ns
tFST
width of SE0 interval during differ-
ential transition
--14
ns



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