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PR533 Datasheet(PDF) 5 Page - NXP Semiconductors |
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PR533 Datasheet(HTML) 5 Page - NXP Semiconductors |
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5 / 36 page  PR533_SDS All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product short data sheet COMPANY PUBLIC Rev. 3.6 — 27 October 2014 206436 5 of 36 NXP Semiconductors PR533 USB NFC integrated reader solution 6. Pinning information 6.1 Pinning 6.2 Pin description Fig 2. Pin configuration for HVQFN 40 (SOT618-1) aaa-000044 PR533 P70_IRQ VMID RX RSTOUT_N AVDD DVSS TVSS2 DM TX2 DP TVDD PVDD TX1 DELATT TVSS1 P30 LOADMOD P31 DVSS P32_INT0 10 21 9 22 8 23 7 24 6 25 5 26 4 27 3 28 2 29 1 30 terminal 1 index area Transparent top view Table 3. PR533 pin description Symbol Pin Type Pad ref voltage Description DVSS 1 G digital ground LOADMOD 2 O DVDD load modulation output provides digital signal for FeliCa and MIFARE card operating mode TVSS1 3 G transmitter ground: supplies the output stage of TX1 TX1 4 O TVDD transmitter 1: transmits modulated 13.56 MHz energy carrier TVDD 5 P transmitter power supply: supplies the output stage of TX1 and TX2 TX2 6 O TVDD transmitter 2: delivers the modulated 13.56 MHz energy carrier TVSS2 7 G transmitter ground: supplies the output stage of TX2 AVDD 8 P analog power supply VMID 9 P AVDD internal reference voltage: This pin delivers the internal reference voltage. RX 10 I AVDD receiver input: Input pin for the reception signal, which is the load modulated 13.56 MHz energy carrier from the antenna circuit AVSS 11 G analog ground AUX1 12 O DVDD auxiliary output 1: This pin delivers analog and digital test signals AUX2 13 O DVDD auxiliary output 2: This pin delivers analog and digital test signals DVSS 14 G digital ground |
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