SA614A

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© NXP B.V. 2014. All rights reserved.

Product data sheet

Rev. 4 — 14 February 2014

11 of 28

NXP Semiconductors

SA614A

Low power FM IF system

13.2 IF amplifiers

The IF amplifier section consists of two log-limiting stages. The first consists of two

differential amplifiers with 39 dB of gain and a small signal bandwidth of 41 MHz (when

driven from a 50

 source). The output of the first limiter is a low impedance emitter

follower with 1 k

 of equivalent series resistance. The second limiting stage consists of

three differential amplifiers with a gain of 62 dB and a small signal AC bandwidth of

28 MHz. The outputs of the final differential stage are buffered to the internal quadrature

detector. One of the outputs is available at pin LIMITER_OUTPUT to drive an external

quadrature capacitor and L/C quadrature tank.

Both of the limiting amplifier stages are DC biased using feedback. The buffered output of

the final differential amplifier is fed back to the input through 42 k

resistors. As shown in

Figure 4, the input impedance is established for each stage by tapping one of the

feedback resistors 1.6 k

 from the input. It requires one additional decoupling capacitor

from the tap point to ground.

Fig 8.

First limiter bias

Fig 9.

Second limiter and quadrature detector

aaa-009978

700 Ω

7 kΩ

42 kΩ

40 kΩ

1.6 kΩ

V+

14

15

16

1

aaa-009762

9V+

8

11

12

10

42 kΩ

40 kΩ

80 kΩ

40 kΩ

Fig 10. Feedback paths

aaa-009763

BPF

BPF