Preliminary Technical Data

AD7933/AD7934

Table 9. Analog Input Type Selection

Channel Address

MODE0 = 0, MODE1 = 0

MODE0 = 0, MODE1 = 1

MODE0 = 1, MODE1 = 0

MODE0 = 1, MODE1 = 1

Four Single-Ended I/P

Channels

Two Fully Differential

I/P Channels

Two Pseudo-Differential

I/P Channels

Not Used

ADD1

ADD0

0

0

VIN0

AGND

VIN0

VIN1

VIN0

VIN1

0

1

VIN1

AGND

VIN1

VIN0

VIN1

VIN0

1

0

VIN2

AGND

VIN2

VIN3

VIN2

VIN3

1

1

VIN3

AGND

VIN3

VIN2

VIN3

VIN2

SEQUENCER OPERATION

The configuration of the SEQ0 and SEQ1 bits in the control register allow the user to use the sequencer function. T

outlines the

two sequencer modes of operation.

able 10

Table 10. Sequence Selection Modes

SEQ0

SEQ1

Sequence Type

0

0

This configuration is selected when the sequence function is not used. The analog input channel selected on each

individual conversion is determined by the contents of the channel address bits, ADD1 and ADD0, in each prior write

operation. This mode of operation reflects the normal operation of a multichannel ADC, without the sequencer function

being used, where each write to the AD7933/AD7934 selects the next channel for conversion.

0

1

Not Used.

1

0

Not Used.

1

1

This configuration is used in conjunction with the channel address bits, ADD1 and ADD0, to program continuous

conversions on a consecutive sequence of channels from Channel 0 through to a selected final channel as determined by

the channel address bits in the control register. When in differential or pseudo-differential mode, inverse channels (e.g.,

VIN1, VIN0) are not converted in this mode.

Rev. PrG | Page 17 of 32