AD7933 datasheet(29/32 Pages) AD

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Preliminary Technical Data

AD7933/AD7934

AD7933/AD7934 to TMS32020, TMS320C25, and

TMS320C5x Interface

Parallel interfaces between the AD7933/AD7934 and the

TMS32020, TMS320C25 and TMS320C5x family of DSPs are

shown in

. The memory mapped address chosen for

the AD7933/AD7934 should be chosen to fall in the I/O

memory space of the DSPs. The parallel interface on the

AD7933/AD7934 is fast enough to interface to the TMS32020

with no extra wait states. If high speed glue logic, such as 74AS

devices, are used to drive the RD and the WR lines when

interfacing to the TMS320C25, then again, no wait states are

necessary. However, if slower logic is used, data accesses may be

slowed sufficiently when reading from and writing to the part to

require the insertion of one wait state. Extra wait states will be

necessary when using the TMS320C5x at their fastest clock

speeds (see the TMS320C5x User’s Guide for details).

Figure 46

Figure 46. Interfacing to the TMS32020/C25/C5x

Data is read from the ADC using the following instruction:

IN D, ADC

where D is the data memory address, and ADC is the

AD7933/AD7934 address.

AD7933/

AD7934*

TMS32020/

TMS320C25/

TMS320C50*

DB11 TO DB0

DMD0 TO DMD15

A0 TO A15

READY

INTX

BUSY

CONVST

OPTIONAL

TMS320C25

ONLY

R/W

STRB

*ADDITIONAL PINS OMITTED FOR CLARITY

ADDRESS BUS

DATA BUS

ADDRESS

DECODER

MSC

AD7933/AD7934 to 80C186 Interface

Figure 47 shows the AD7933/AD7934 interfaced to the 80C186

microprocessor. The 80C186 DMA controller provides two

independent high speed DMA channels where data transfer can

occur between memory and I/O spaces. Each data transfer

consumes two bus cycles, one cycle to fetch data and the other

to store data. After the AD7933/AD7934 has finished a

conversion, the BUSY line generates a DMA request to

Channel 1 (DRQ1). As a result of the interrupt, the processor

performs a DMA READ operation which also resets the

interrupt latch. Sufficient priority must be assigned to the DMA

channel to ensure that the DMA request will be serviced before

the completion of the next conversion.

AD7933/

AD7934*

80C186*

DB0 TO DB11

AD0 TO AD15

A16 TO A19

ALE

DRQ1

BUSY

CONVST

OPTIONAL

*ADDITIONAL PINS OMITTED FOR CLARITY

ADDRESS/DATA BUS

ADDRESS BUS

DATA BUS

ADDRESS

LATCH

ADDRESS

DECODER

Figure 47. Interfacing to the 80C186

Rev. PrG | Page 29 of 32

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