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AD7933/AD7934

Preliminary Technical Data

Digital Inputs

PARALLEL INTERFACE

The digital inputs applied to the AD7933/AD7934 are not

limited by the maximum ratings that limit the analog inputs.

Instead, the digital inputs applied can go to 7 V and are not

restricted by the AVDD + 0.3 V limit that is on the analog inputs.

The AD7933/AD7934 have a flexible, high speed, parallel

interface. This interface is 12-bits (AD7934) or 10-bits

(AD7933) wide and is capable of operating in either word (W/B

tied high) or byte (W/B tied low) mode. The CONVST signal is

used to initiate conversions, and when operating in auto

shutdown or auto standby mode, it is used to power up the

ADC.

Another advantage of the digital inputs not being restricted by

the AVDD + 0.3 V limit is the fact that power supply sequencing

issues are avoided. If any of these inputs are applied before AVDD,

then there is no risk of latch-up as there would be on the analog

inputs if a signal greater than 0.3 V was applied prior to AVDD.

A falling edge on the CONVST signal is used to initiate

conversions, and it also puts the ADC track-and-hold into track.

Once the CONVST signal goes low, the BUSY signal goes high

for the duration of the conversion. In between conversions,

CONVST must be brought high for a minimum time of t1. This

must happen after the 14th rising edge of CLKIN; otherwise, the

conversion will be aborted and the track-and-hold will go back

into track. At the end of the conversion, BUSY goes low and can

be used to activate an interrupt service routine. The CS and RD

lines are then activated in parallel to read the 12 bits or 10 bits

of conversion data. When power supplies are first applied to the

device, a rising edge on CONVST puts the track-and-hold into

track. The acquisition time of 135 ns minimum must be allowed

before CONVST is brought low to initiate a conversion. The

ADC will then go into hold on the falling edge of CONVST and

back into track on the 13th rising edge of CLKIN after this (see

). When operating the device in auto shutdown or auto

standby mode, where the ADC powers down at the end of each

conversion, a rising edge on the CONVST signal is used to

power up the device.

VDRIVE Input

The AD7933/AD7934 has a VDRIVE feature. VDRIVE controls the

voltage at which the parallel interface operates. VDRIVE allows the

ADC to easily interface to 1.8 V, 3 V, and 5 V processors. VDRIVE

of 1.8 V can only be used if VDD = 2.7 V to 3.6 V.

For example, if the AD7933/AD7934 operated with an AVDD of

5 V and the VDRIVE pin could be powered from a 3 V supply, the

AD7933/AD7934 has better dynamic performance with an

AVDD of 5 V while still being able to interface to 3 V processors.

Care should be taken to ensure VDRIVE does not exceed AVDD by

more than 0.3 V (see

Table 4

Figure 37

Figure 37. AD7933/AD7934 Parallel Interface—Conversion and Read Cycle in Word Mode (W/B = 1)

t20

t14

t11

t13

t12

t10

tCONVERT

tAQUISITION

tQUIET

DATA

OLD DATA

DB0 TO DB11

INTERNAL

TRACK/HOLD

BUSY

CLKIN

CONVST

THREE-STATE

WITH CS AND RD TIED LOW

Rev. PrG | Page 24 of 32

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