AD7933 datasheet(18/32 Pages) AD

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AD7933/AD7934

Preliminary Technical Data

CIRCUIT INFORMATION

The AD7933/AD7934 are fast, 4-channel, 12-bit and10-bit,

single-supply, successive approximation analog-to-digital

converters. The parts operate from either a 2.7 V to 3.6 V or

4.75 V to 5.25 V power supply and feature throughput rates up

to 1.5 MSPS.

When the ADC starts a conversion (Figure 19), SW3 will open

and SW1 and SW2 will move to Position B, causing the

comparator to become unbalanced. Both inputs are

disconnected once the conversion begins. The control logic and

charge redistribution DACs are used to add and subtract fixed

amounts of charge from the sampling capacitor arrays to bring

the comparator back into a balanced condition. When the

comparator is rebalanced, the conversion is complete. The

control logic generates the ADC’s output code. The output

impedances of the sources driving the VIN+ and the VIN− pins

must be matched; otherwise, the two inputs will have different

settling times, resulting in errors.

The AD7933/AD7934 provide the user with an on-chip track-

and-hold, an internal accurate reference, an analog-to-digital

converter, and a parallel interface housed in a 28-lead TSSOP

package.

The AD7933/AD7934 have four analog input channels that can

be configured to be four single-ended inputs, two fully

differential pairs, or two pseudo-differential pairs. There is an

on-chip channel sequencer that allows the user to select a

consecutive sequence of channels through which the ADC can

cycle with each falling edge of CONVST.

VIN+

VIN–

SW1

SW3

COMPARATOR

CONTROL

LOGIC

CAPACITIVE

DAC

CAPACITIVE

DAC

VREF

SW2

The analog input range for the AD7933/AD7934 is 0 to VREF or

0 to 2 × VREF, depending on the status of the RANGE bit in the

control register. The output coding of the ADC can be either

binary or twos complement, depending on the status of the

CODING bit in the control register.

Figure 19. ADC Conversion Phase

ADC TRANSFER FUNCTION

The AD7933/AD7934 provide flexible power management

options to allow users to achieve the best power performance

for a given throughput rate. These options are selected by

programming the power management bits, PM1 and PM0, in

the control register.

The output coding for the AD7933/AD7934 is either straight

binary or twos complement, depending on the status of the

CODING bit in the control register. The designed code

transitions occur at successive LSB values (i.e., 1 LSB, 2 LSBs,

and so on) and the LSB size is VREF/1024 for the AD7933 and

VREF/4096 for the AD7934. The ideal transfer characteristics of

the AD7933/AD7934 for both straight binary and twos

complement output coding are shown in Figure 20 and Figure 21,

respectively.

CONVERTER OPERATION

The AD7933/AD7934 are a successive approximation ADC

based on two capacitive DACs. Figure 18 and Figure 19 show

simplified schematics of the ADC in acquisition and conversion

phase, respectively. The ADC comprises of control logic, a SAR,

and two capacitive DACs. Both figures show the operation of

the ADC in differential/pseudo-differential mode. Single-ended

mode operation is similar but VIN− is internally tied to AGND.

In the acquisition phase, SW3 is closed, SW1 and SW2 are in

Position A, the comparator is held in a balanced condition, and

the sampling capacitor arrays acquire the differential signal on

the input.

000...000

111...111

1 LSB = VREF/4096 (AD7934)

1 LSB = VREF/1024 (AD7933)

1 LSB

+VREF–1 LSB

ANALOG INPUT

NOTE: VREF IS EITHER VREF OR 2 × VREF

000...001

000...010

111...110

111...000

011...111

VIN+

VIN–

SW1

SW3

COMPARATOR

CONTROL

LOGIC

CAPACITIVE

DAC

CAPACITIVE

DAC

VREF

SW2

Figure 20. AD7933/AD7934 Ideal Transfer Characteristic

with Straight Binary Output Coding

Figure 18. ADC Acquisition Phase

Rev. PrG | Page 18 of 32

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