AD7933 datasheet(28/32 Pages) AD

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AD7933/AD7934

Preliminary Technical Data

POWER VS. THROUGHPUT RATE

A big advantage of powering the ADC down after a conversion

is that the power consumption of the part is significantly

reduced at lower throughput rates. When using the different

power modes, the AD7933/AD7934 is only powered up for the

duration of the conversion. Therefore, the average power

consumption per cycle is significantly reduced. F

and

show plots of the power versus the throughput when

operating in auto shutdown and auto standby modes.

igure 42

Figure 42. Power vs. Throughput in Auto Shutdown Mode

Figure 43

Figure 43. Power vs. Throughput in Auto Standby Mode

MICROPROCESSOR INTERFACING

AD7933/AD7934 to ADSP-21xx Interface

Figure 44

Figure 44. Interfacing to the ADSP-21xx

shows the AD7933/AD7934 interfaced to the ADSP-

21xx series of DSPs as a memory mapped device. A single wait

state may be necessary to interface the AD7933/AD7934 to the

ADSP-21xx, depending on the clock speed of the DSP. The wait

state can be programmed via the data memory wait state

control register of the ADSP-21xx (see the ADSP-21xx family

User’s Manual for details). The following instruction reads from

the AD7933/AD7934:

MR = DM (ADC)

where ADC is the address of the AD7933/AD7934.

AD7933/

AD7934*

ADSP-21xx*

DB0 TO DB11

D0 TO D23

A0 TO A15

DMS

IRQ2

BUSY

CONVST

OPTIONAL

*ADDITIONAL PINS OMITTED FOR CLARITY

ADDRESS BUS

DATA BUS

ADDRESS

DECODER

AD7933/AD7934 to ADSP-21065L Interface

Figure 45

Figure 45. Interfacing to the ADSP-21065L

shows a typical interface between the

AD7933/AD7934 and the ADSP-21065L SHARC processor.

This interface is an example of one of three DMA handshake

modes. The MSx control line is actually three memory select

lines. Internal ADDR25–24 are decoded into MS3-0, these lines are

then asserted as chip selects. The DMAR1 (DMA request 1) is

used in this setup as the interrupt to signal the end of the

conversion. The rest of the interface is standard handshaking

operation.

AD7933/

AD7934*

ADSP-21065L*

DB0 TO DB11

D0 TO D31

ADDR0 TO ADDR23

MSX

DMAR1

BUSY

CONVST

OPTIONAL

*ADDITIONAL PINS OMITTED FOR CLARITY

ADDRESS BUS

DATA BUS

ADDRESS

LATCH

ADDRESS

DECODER

Rev. PrG | Page 28 of 32

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