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Preliminary Technical Data

AD7933/AD7934

ANALOG INPUT STRUCTURE

100...000

011...111

1 LSB = 2

× VREF/4096 (AD7934)

1 LSB = 2

× VREF/1024 (AD7933)

–VREF + 1 LSB

VREF

+VREFV – 1 LSB

100...001

100...010

011...110

000...001

000...000

111...111

Figure 23 shows the equivalent circuit of the analog input

structure of the AD7933/AD7934 in differential/pseudo-

differential mode. In single-ended mode, VIN− is internally tied

to AGND. The four diodes provide ESD protection for the

analog inputs. Care must be taken to ensure that the analog

input signals never exceed the supply rails by more than

300 mV. This causes these diodes to become forward-biased and

start conducting into the substrate. These diodes can conduct

up to 10 mA without causing irreversible damage to the part.

The C1 capacitors, in Figure 23, are typically 4 pF and can

primarily be attributed to pin capacitance. The resistors are

lumped components made up of the on resistance of the

switches. The value of these resistors is typically about 100 Ω.

The C2 capacitors, in Figure 23, are the ADC’s sampling

capacitors and have a typical capacitance of 16 pF.

Figure 21. AD7933/AD7934 Ideal Transfer Characteristic

with Twos Complement Output Coding

TYPICAL CONNECTION DIAGRAM

Figure 22

Figure 22. Typical Connection Diagram

shows a typical connection diagram for the

AD7933/AD7934. The AGND and DGND pins are connected

together at the device for good noise suppression. The

VREFIN/VREFOUT pin is decoupled to AGND with a 0.47 µF

capacitor to avoid noise pickup, if the internal reference is used.

Alternatively, VREFIN/VREFOUT can be connected to a external

reference source, and in this case, the reference pin should be

decoupled with a 0.1 µF capacitor. In both cases, the analog

input range can either be 0 V to VREF (RANGE bit = 0) or 0 V to

2 × VREF (RANGE bit = 1). The analog input configuration is

either four single-ended inputs, two differential pairs or two

pseudo-differential pairs (see

). The VDD pin connects to

either a 3 V or 5 V supply. The voltage applied to the VDRIVE

input controls the voltage of the digital interface, and here, it is

connected to the same 3 V supply of the microprocessor to

allow a 3 V logic interface (see the

section).

For ac applications, removing high frequency components from

the analog input signal is recommended by using an RC low-

pass filter on the relevant analog input pins. In applications

where harmonic distortion and signal-to-noise ratio are critical,

the analog input should be driven from a low impedance source.

Large source impedances significantly affect the ac performance

of the ADC. This may necessitate the use of an input buffer

amplifier. The choice of the op amp is a function of the

particular application.

VIN+

VDD

VIN–

VDD

Table 9

Digital Inputs

0.1

µF10µF

3V/5V

SUPPLY

µC/µP

AD7933/AD7934

0.1

µF

0.1

µF EXTERNAL VREF

0.47

µF INTERNAL VREF

0 TO VREF/

0 TO 2

× VREF

AGND

DGND

W/B

CLKIN

VDRIVE

VIN0

VDD

VREFIN/VREFOUT

VIN3

µF

2.5V

VREF

CONVST

BUSY

DB0

DB11/DB9

Figure 23. Equivalent Analog Input Circuit, Conversion Phase—Switches,

Open Track Phase—Switches Closed

When no amplifier is used to drive the analog input, the source

impedance should be limited to low values. The maximum

source impedance will depend on the amount of THD that can

be tolerated. The THD increases as the source impedance

increases and performance degrades. F

shows a graph of

the THD versus the analog input signal frequency for different

source impedances for both VDD = 5 V and 3 V.

igure 24

Rev. PrG | Page 19 of 32

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