AMC7823 datasheet(19/48 Pages) TI

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APPLICATION INFORMATION

DIGITAL INTERFACE

AMC7823 COMMUNICATION PROTOCOL

AMC7823

SLAS453A – APRIL 2005 – REVISED OCTOBER 2005

The AMC7823 communicates through a standard SPI bus. The SPI allows full-duplex, synchronous, serial

communication between a host processor (the master) and peripheral devices (slaves). The SPI master

generates the synchronizing clock and initiates transmissions. SPI slave devices, such as the AMC7823, depend

on a master to start and synchronize transmissions.

A transmission begins when initiated by an SPI master. A word from the master is shifted into the AMC7823

through the MOSI pin under the control of the master serial clock, SCLK. A word from an AMC7823 register is

shifted out from the MISO pin under the control of SCLK as well.

The idle state of the serial clock for the AMC7823 is low, which corresponds to a clock polarity setting of 0

(typical microprocessor SPI control bit CPOL = 0). The AMC7823 interface is designed with a clock phase setting

of 1 (typical microprocessor SPI control bit CPHA = 1). In both the master and slave, the data is shifted out on

the rising edge of SCLK and sampled on the falling edge of SCLK where data is stable. The master begins

driving the MOSI pin on the first rising edge of SCLK after SS is activated (low).

To write data into AMC7823, the host activates the slave select signal (SS = low) and issues a WRITE command

to start the data transmission. The AMC7823 always interprets the first word (from the host) immediately

following the falling edge of SS signal as a command. The data to be written into the AMC7823 follow the

command. The slave select pin (SS) must remain low until all data are transmitted (see Figure 39). Otherwise,

the WRITE operation is terminated. Likewise, to read data from AMC7823, the host activates the slave select

signal and sends a READ command. The AMC7823 then sends data out through the MISO pin under the control

of SCLK. The slave select pin must remain low until all data are shifted out (see Figure 39). Otherwise, the

transmission is terminated, and all remaining data (if any) are ignored.

When the operation is terminated, the master must issue a new command to start a new operation.

All registers in the AMC7823 are 16-bit. It takes 16 clock pulses of SCLK to transfer one data or command word.

All data are transferred into (or out of) the AMC7823 through an internal serial-parallel (parallel-serial) register. If

SS is deactivated (that is, goes high) before the 16th clock finishes, the incomplete transfer is terminated

immediately and the data being transferred are ignored. In a write operation, this data is not written into the

AMC7823 register. In a read operation, the remaining data bits are not shifted out, and the data must be ignored.

With the exception of two external trigger pins, an external RESET pin, and an external current setting resistor,

the AMC7823 is entirely controlled by registers. Reading from and writing to these registers is accomplished by

issuing a 16-bit command word followed immediately by data for a single register or for a range of registers. This

command word is constructed as shown in the Bit Register. The data word(s) format for the target register(s) are

illustrated in subsequent pages of this document.

Bit Register

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MSB

LSB

R/W

PG1

PG0

SADR4

SADR3

SADR2

SADR1

SADR0

EADR4

EADR3

EADR2

EADR1

EADR0

X : Don't Care

Where:

R/W: Data flow direction bit.

R/W = 1. Read operation. Data is transferred from AMC7823 to the host.

R/W = 0. Write operation. Data is transferred from the host to AMC7823.

PG1 – PG0: Memory page of addressed register(s) (see Table 1).

SADR4 – SADR0: Starting address of register(s) on selected page.

EADR4 – EADR0: Ending address of register(s) on selected page.

AMC7823 Datasheet(PDF) 19 Page - Texas Instruments

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